From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 15E7CCCFA13 for ; Fri, 1 May 2026 13:17:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 604E410E1B7; Fri, 1 May 2026 13:17:30 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=arm.com header.i=@arm.com header.b="JV9nlnNs"; dkim-atps=neutral Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by gabe.freedesktop.org (Postfix) with ESMTP id 7A1EB10E1B7 for ; Fri, 1 May 2026 13:17:29 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8D43C176A; Fri, 1 May 2026 06:17:23 -0700 (PDT) Received: from [10.1.29.19] (e122027.cambridge.arm.com [10.1.29.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 86B553F62B; Fri, 1 May 2026 06:17:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1777641449; bh=4RGQVSM/Z48u+dPA3KGZkZ7imj1yU7dBhhrjJzYt8oc=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=JV9nlnNstUK/BjjHpzC9JxesqXFPcZwf4mjBjIJ5J3fbS+n3AUI3dTWtaxu3tNiJG v0BzjvJ7C10mnunxeyqTZ7JcvdiY2H5g+3Mu+ZeZoK3JsxcZh3rnRJT4YIq2vSYOYZ MjEeJTXpwcZmyY5RgCePs/LU2vJ2kJPpPzOVvk10= Message-ID: <9b4653e7-bb88-4b0f-a620-5fe74e6c0c51@arm.com> Date: Fri, 1 May 2026 14:17:21 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 02/10] drm/panthor: Move the register accessors before the IRQ helpers To: Boris Brezillon , Liviu Dudau Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20260429-panthor-signal-from-irq-v1-0-4b92ae4142d2@collabora.com> <20260429-panthor-signal-from-irq-v1-2-4b92ae4142d2@collabora.com> From: Steven Price Content-Language: en-GB In-Reply-To: <20260429-panthor-signal-from-irq-v1-2-4b92ae4142d2@collabora.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 29/04/2026 10:38, Boris Brezillon wrote: > We're about to add an IRQ inline helper using gpu_read(). Move things > around to avoid forward declarations. > > No functional changes. > > Signed-off-by: Boris Brezillon Reviewed-by: Steven Price > --- > drivers/gpu/drm/panthor/panthor_device.h | 142 +++++++++++++++---------------- > 1 file changed, 71 insertions(+), 71 deletions(-) > > diff --git a/drivers/gpu/drm/panthor/panthor_device.h b/drivers/gpu/drm/panthor/panthor_device.h > index 3f91ba73829d..768fc1992368 100644 > --- a/drivers/gpu/drm/panthor/panthor_device.h > +++ b/drivers/gpu/drm/panthor/panthor_device.h > @@ -495,6 +495,77 @@ panthor_exception_is_fault(u32 exception_code) > const char *panthor_exception_name(struct panthor_device *ptdev, > u32 exception_code); > > +static inline void gpu_write(void __iomem *iomem, u32 reg, u32 data) > +{ > + writel(data, iomem + reg); > +} > + > +static inline u32 gpu_read(void __iomem *iomem, u32 reg) > +{ > + return readl(iomem + reg); > +} > + > +static inline u32 gpu_read_relaxed(void __iomem *iomem, u32 reg) > +{ > + return readl_relaxed(iomem + reg); > +} > + > +static inline void gpu_write64(void __iomem *iomem, u32 reg, u64 data) > +{ > + gpu_write(iomem, reg, lower_32_bits(data)); > + gpu_write(iomem, reg + 4, upper_32_bits(data)); > +} > + > +static inline u64 gpu_read64(void __iomem *iomem, u32 reg) > +{ > + return (gpu_read(iomem, reg) | ((u64)gpu_read(iomem, reg + 4) << 32)); > +} > + > +static inline u64 gpu_read64_relaxed(void __iomem *iomem, u32 reg) > +{ > + return (gpu_read_relaxed(iomem, reg) | > + ((u64)gpu_read_relaxed(iomem, reg + 4) << 32)); > +} > + > +static inline u64 gpu_read64_counter(void __iomem *iomem, u32 reg) > +{ > + u32 lo, hi1, hi2; > + do { > + hi1 = gpu_read(iomem, reg + 4); > + lo = gpu_read(iomem, reg); > + hi2 = gpu_read(iomem, reg + 4); > + } while (hi1 != hi2); > + return lo | ((u64)hi2 << 32); > +} > + > +#define gpu_read_poll_timeout(iomem, reg, val, cond, delay_us, timeout_us) \ > + read_poll_timeout(gpu_read, val, cond, delay_us, timeout_us, false, \ > + iomem, reg) > + > +#define gpu_read_poll_timeout_atomic(iomem, reg, val, cond, delay_us, \ > + timeout_us) \ > + read_poll_timeout_atomic(gpu_read, val, cond, delay_us, timeout_us, \ > + false, iomem, reg) > + > +#define gpu_read64_poll_timeout(iomem, reg, val, cond, delay_us, timeout_us) \ > + read_poll_timeout(gpu_read64, val, cond, delay_us, timeout_us, false, \ > + iomem, reg) > + > +#define gpu_read64_poll_timeout_atomic(iomem, reg, val, cond, delay_us, \ > + timeout_us) \ > + read_poll_timeout_atomic(gpu_read64, val, cond, delay_us, timeout_us, \ > + false, iomem, reg) > + > +#define gpu_read_relaxed_poll_timeout_atomic(iomem, reg, val, cond, delay_us, \ > + timeout_us) \ > + read_poll_timeout_atomic(gpu_read_relaxed, val, cond, delay_us, \ > + timeout_us, false, iomem, reg) > + > +#define gpu_read64_relaxed_poll_timeout(iomem, reg, val, cond, delay_us, \ > + timeout_us) \ > + read_poll_timeout(gpu_read64_relaxed, val, cond, delay_us, timeout_us, \ > + false, iomem, reg) > + > #define INT_RAWSTAT 0x0 > #define INT_CLEAR 0x4 > #define INT_MASK 0x8 > @@ -629,75 +700,4 @@ static inline void panthor_ ## __name ## _irq_disable_events(struct panthor_irq > > extern struct workqueue_struct *panthor_cleanup_wq; > > -static inline void gpu_write(void __iomem *iomem, u32 reg, u32 data) > -{ > - writel(data, iomem + reg); > -} > - > -static inline u32 gpu_read(void __iomem *iomem, u32 reg) > -{ > - return readl(iomem + reg); > -} > - > -static inline u32 gpu_read_relaxed(void __iomem *iomem, u32 reg) > -{ > - return readl_relaxed(iomem + reg); > -} > - > -static inline void gpu_write64(void __iomem *iomem, u32 reg, u64 data) > -{ > - gpu_write(iomem, reg, lower_32_bits(data)); > - gpu_write(iomem, reg + 4, upper_32_bits(data)); > -} > - > -static inline u64 gpu_read64(void __iomem *iomem, u32 reg) > -{ > - return (gpu_read(iomem, reg) | ((u64)gpu_read(iomem, reg + 4) << 32)); > -} > - > -static inline u64 gpu_read64_relaxed(void __iomem *iomem, u32 reg) > -{ > - return (gpu_read_relaxed(iomem, reg) | > - ((u64)gpu_read_relaxed(iomem, reg + 4) << 32)); > -} > - > -static inline u64 gpu_read64_counter(void __iomem *iomem, u32 reg) > -{ > - u32 lo, hi1, hi2; > - do { > - hi1 = gpu_read(iomem, reg + 4); > - lo = gpu_read(iomem, reg); > - hi2 = gpu_read(iomem, reg + 4); > - } while (hi1 != hi2); > - return lo | ((u64)hi2 << 32); > -} > - > -#define gpu_read_poll_timeout(iomem, reg, val, cond, delay_us, timeout_us) \ > - read_poll_timeout(gpu_read, val, cond, delay_us, timeout_us, false, \ > - iomem, reg) > - > -#define gpu_read_poll_timeout_atomic(iomem, reg, val, cond, delay_us, \ > - timeout_us) \ > - read_poll_timeout_atomic(gpu_read, val, cond, delay_us, timeout_us, \ > - false, iomem, reg) > - > -#define gpu_read64_poll_timeout(iomem, reg, val, cond, delay_us, timeout_us) \ > - read_poll_timeout(gpu_read64, val, cond, delay_us, timeout_us, false, \ > - iomem, reg) > - > -#define gpu_read64_poll_timeout_atomic(iomem, reg, val, cond, delay_us, \ > - timeout_us) \ > - read_poll_timeout_atomic(gpu_read64, val, cond, delay_us, timeout_us, \ > - false, iomem, reg) > - > -#define gpu_read_relaxed_poll_timeout_atomic(iomem, reg, val, cond, delay_us, \ > - timeout_us) \ > - read_poll_timeout_atomic(gpu_read_relaxed, val, cond, delay_us, \ > - timeout_us, false, iomem, reg) > - > -#define gpu_read64_relaxed_poll_timeout(iomem, reg, val, cond, delay_us, \ > - timeout_us) \ > - read_poll_timeout(gpu_read64_relaxed, val, cond, delay_us, timeout_us, \ > - false, iomem, reg) > - > #endif >