Re: [PATCH 12/16] drm/msm/a6xx: Add SKU detection support for X2-85

[Rob Clark <rob.clark@oss.qualcomm.com>]

On Mon, Mar 23, 2026 at 1:13 PM Akhil P Oommen <akhilpo@oss.qualcomm.com> wrote:
>
> Adreno X2-85 series present in Glymur chipset supports a new mechanism
> for SKU detection. A new CX_MISC register exposes the combined (or
> final) speedbin value from both HW fuse register and the Soft Fuse
> register.
>
> Implement this new SKU detection along with a new quirk to identify the
> GPUs that has SOFT SKU support. Also, enable this quirk for Adreno X2-85
> and add its SKU table to the catalog.
>
> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> ---
>  drivers/gpu/drm/msm/adreno/a5xx_gpu.c         |  6 ++++
>  drivers/gpu/drm/msm/adreno/a6xx_catalog.c     |  9 +++++-
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.c         | 41 ++++++++++++++++++++++-----
>  drivers/gpu/drm/msm/adreno/adreno_gpu.c       |  5 ----
>  drivers/gpu/drm/msm/adreno/adreno_gpu.h       |  1 +
>  drivers/gpu/drm/msm/registers/adreno/a6xx.xml |  4 +++
>  6 files changed, 53 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> index 79a441e91fa1..d7ed3225f635 100644
> --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> @@ -1731,6 +1731,7 @@ static struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
>         struct adreno_gpu *adreno_gpu;
>         struct msm_gpu *gpu;
>         unsigned int nr_rings;
> +       u32 speedbin;
>         int ret;
>
>         a5xx_gpu = kzalloc(sizeof(*a5xx_gpu), GFP_KERNEL);
> @@ -1757,6 +1758,11 @@ static struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
>                 return ERR_PTR(ret);
>         }
>
> +       /* Set the speedbin value that is passed to userspace */
> +       if (adreno_read_speedbin(&pdev->dev, &speedbin) || !speedbin)
> +               speedbin = 0xffff;
> +       adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
> +

I will confess to not expecting to see a5xx changes in a patch adding
x2-85 sku detection :-)

Maybe split the code-motion out of adreno_gpu_init() into it's own commit?

BR,
-R

>         msm_mmu_set_fault_handler(to_msm_vm(gpu->vm)->mmu, gpu,
>                                   a5xx_fault_handler);
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> index f6b9792531a6..758bc7bd31f6 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> @@ -1902,7 +1902,8 @@ static const struct adreno_info a8xx_gpus[] = {
>                 .gmem = 21 * SZ_1M,
>                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
>                 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
> -                         ADRENO_QUIRK_HAS_HW_APRIV,
> +                         ADRENO_QUIRK_HAS_HW_APRIV |
> +                         ADRENO_QUIRK_SOFTFUSE,
>                 .funcs = &a8xx_gpu_funcs,
>                 .a6xx = &(const struct a6xx_info) {
>                         .protect = &x285_protect,
> @@ -1922,6 +1923,12 @@ static const struct adreno_info a8xx_gpus[] = {
>                                 { /* sentinel */ },
>                         },
>                 },
> +               .speedbins = ADRENO_SPEEDBINS(
> +                       { 0,   0 },
> +                       { 388, 1 },
> +                       { 357, 2 },
> +                       { 284, 3 },
> +               ),
>         }, {
>                 .chip_ids = ADRENO_CHIP_IDS(0x44050a01),
>                 .family = ADRENO_8XX_GEN2,
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index cbc803d90673..0fe6d803e628 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -2552,13 +2552,33 @@ static u32 fuse_to_supp_hw(const struct adreno_info *info, u32 fuse)
>         return UINT_MAX;
>  }
>
> -static int a6xx_set_supported_hw(struct device *dev, const struct adreno_info *info)
> +static int a6xx_read_speedbin(struct device *dev, struct a6xx_gpu *a6xx_gpu,
> +               const struct adreno_info *info, u32 *speedbin)
> +{
> +       int ret;
> +
> +       /* Use speedbin fuse if present. Otherwise, fallback to softfuse */
> +       ret = adreno_read_speedbin(dev, speedbin);
> +       if (ret != -ENOENT)
> +               return ret;
> +
> +       if (info->quirks & ADRENO_QUIRK_SOFTFUSE) {
> +               *speedbin = a6xx_llc_read(a6xx_gpu, REG_A8XX_CX_MISC_SW_FUSE_FREQ_LIMIT_STATUS);
> +               *speedbin = A8XX_CX_MISC_SW_FUSE_FREQ_LIMIT_STATUS_FINALFREQLIMIT(*speedbin);
> +               return 0;
> +       }
> +
> +       return -ENOENT;
> +}
> +
> +static int a6xx_set_supported_hw(struct device *dev, struct a6xx_gpu *a6xx_gpu,
> +               const struct adreno_info *info)
>  {
>         u32 supp_hw;
>         u32 speedbin;
>         int ret;
>
> -       ret = adreno_read_speedbin(dev, &speedbin);
> +       ret = a6xx_read_speedbin(dev, a6xx_gpu, info, &speedbin);
>         /*
>          * -ENOENT means that the platform doesn't support speedbin which is
>          * fine
> @@ -2592,11 +2612,13 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
>         struct msm_drm_private *priv = dev->dev_private;
>         struct platform_device *pdev = priv->gpu_pdev;
>         struct adreno_platform_config *config = pdev->dev.platform_data;
> +       const struct adreno_info *info = config->info;
>         struct device_node *node;
>         struct a6xx_gpu *a6xx_gpu;
>         struct adreno_gpu *adreno_gpu;
>         struct msm_gpu *gpu;
>         extern int enable_preemption;
> +       u32 speedbin;
>         bool is_a7xx;
>         int ret, nr_rings = 1;
>
> @@ -2619,14 +2641,14 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
>         adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, "qcom,adreno-gmu-wrapper");
>
>         adreno_gpu->base.hw_apriv =
> -               !!(config->info->quirks & ADRENO_QUIRK_HAS_HW_APRIV);
> +               !!(info->quirks & ADRENO_QUIRK_HAS_HW_APRIV);
>
>         /* gpu->info only gets assigned in adreno_gpu_init(). A8x is included intentionally */
> -       is_a7xx = config->info->family >= ADRENO_7XX_GEN1;
> +       is_a7xx = info->family >= ADRENO_7XX_GEN1;
>
>         a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx);
>
> -       ret = a6xx_set_supported_hw(&pdev->dev, config->info);
> +       ret = a6xx_set_supported_hw(&pdev->dev, a6xx_gpu, info);
>         if (ret) {
>                 a6xx_llc_slices_destroy(a6xx_gpu);
>                 kfree(a6xx_gpu);
> @@ -2634,15 +2656,20 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
>         }
>
>         if ((enable_preemption == 1) || (enable_preemption == -1 &&
> -           (config->info->quirks & ADRENO_QUIRK_PREEMPTION)))
> +           (info->quirks & ADRENO_QUIRK_PREEMPTION)))
>                 nr_rings = 4;
>
> -       ret = adreno_gpu_init(dev, pdev, adreno_gpu, config->info->funcs, nr_rings);
> +       ret = adreno_gpu_init(dev, pdev, adreno_gpu, info->funcs, nr_rings);
>         if (ret) {
>                 a6xx_destroy(&(a6xx_gpu->base.base));
>                 return ERR_PTR(ret);
>         }
>
> +       /* Set the speedbin value that is passed to userspace */
> +       if (a6xx_read_speedbin(&pdev->dev, a6xx_gpu, info, &speedbin) || !speedbin)
> +               speedbin = 0xffff;
> +       adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
> +
>         /*
>          * For now only clamp to idle freq for devices where this is known not
>          * to cause power supply issues:
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> index 10d9e5f40640..826661cb7988 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> @@ -1184,7 +1184,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
>         struct msm_gpu_config adreno_gpu_config  = { 0 };
>         struct msm_gpu *gpu = &adreno_gpu->base;
>         const char *gpu_name;
> -       u32 speedbin;
>         int ret;
>
>         adreno_gpu->funcs = funcs;
> @@ -1213,10 +1212,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
>                         devm_pm_opp_set_clkname(dev, "core");
>         }
>
> -       if (adreno_read_speedbin(dev, &speedbin) || !speedbin)
> -               speedbin = 0xffff;
> -       adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
> -
>         gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT,
>                         ADRENO_CHIPID_ARGS(config->chip_id));
>         if (!gpu_name)
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index 29097e6b4253..044ed4d49aa7 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -63,6 +63,7 @@ enum adreno_family {
>  #define ADRENO_QUIRK_PREEMPTION                        BIT(5)
>  #define ADRENO_QUIRK_4GB_VA                    BIT(6)
>  #define ADRENO_QUIRK_IFPC                      BIT(7)
> +#define ADRENO_QUIRK_SOFTFUSE                  BIT(8)
>
>  /* Helper for formating the chip_id in the way that userspace tools like
>   * crashdec expect.
> diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
> index 3941e7510754..2309870f5031 100644
> --- a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
> +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
> @@ -5016,6 +5016,10 @@ by a particular renderpass/blit.
>                 <bitfield pos="1" name="LPAC" type="boolean"/>
>                 <bitfield pos="2" name="RAYTRACING" type="boolean"/>
>         </reg32>
> +       <reg32 offset="0x0405" name="CX_MISC_SW_FUSE_FREQ_LIMIT_STATUS" variants="A8XX-">
> +               <bitfield high="8" low="0" name="FINALFREQLIMIT"/>
> +               <bitfield pos="24" name="SOFTSKUDISABLED" type="boolean"/>
> +       </reg32>
>  </domain>
>
>  </database>
>
> --
> 2.51.0
>