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Mon, 23 Mar 2026 13:38:02 -0700 (PDT) X-Received: by 2002:a05:6820:160b:b0:67d:ee3c:9ad4 with SMTP id 006d021491bc7-67dee3cba9fmr2510222eaf.1.1774298282085; Mon, 23 Mar 2026 13:38:02 -0700 (PDT) MIME-Version: 1.0 References: <20260324-a8xx-gpu-batch2-v1-0-fc95b8d9c017@oss.qualcomm.com> <20260324-a8xx-gpu-batch2-v1-12-fc95b8d9c017@oss.qualcomm.com> In-Reply-To: <20260324-a8xx-gpu-batch2-v1-12-fc95b8d9c017@oss.qualcomm.com> From: Rob Clark Date: Mon, 23 Mar 2026 13:37:50 -0700 X-Gm-Features: AQROBzDynikIebC1QNf7dTP-npSQujbxNMJmxWjLbwDutWftcNbPlmn0jTGkAU0 Message-ID: Subject: Re: [PATCH 12/16] drm/msm/a6xx: Add SKU detection support for X2-85 To: Akhil P Oommen Cc: Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Antonino Maniscalco , Connor Abbott , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=fq7RpV4f c=1 sm=1 tr=0 ts=69c1a4ab cx=c_pps a=V4L7fE8DliODT/OoDI2WOg==:117 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=7z8P23FROURhuZ24mNkA:9 a=QEXdDO2ut3YA:10 a=WZGXeFmKUf7gPmL3hEjn:22 X-Proofpoint-ORIG-GUID: 154_tEb776R1k3oHYgUoz2qjThyD5yUu X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzIzMDE1MiBTYWx0ZWRfXxZq5ksYHeif4 jU0MfjrYaC6mv1ygrqEEbMs9yFS7sTBVFEC9U1/M8FmflB3AJGEPZ1GzlpboJ9p0ahdTYNio1fm VqYJNmnPw/j0mAK71xG3j3g89Ai1LAgzgLNScGN6qic9ldp6gqBLjXA6uUfhZjOKflNnON5Oh9v HvdDA0mkQg1tTddR28TfWXWMOPiCt6q3WbcB7juoYb3FBpe03CgXY5vVsPxvY47SUO2z+Xd5eVz Y2GVbLAP8eRx1S+aCZ6AIZOxH2R2NbhKU1v8p3H9KCxOOcEduDAQwg48UT5NlpRWINYDFLgDRQP J3GfOYldyv9xfXsw1ANS5BXzR+u4zp9ySnHEtNpfGq/3tCJMEgFU0Vk8zSefhKRMP/xWtjvSzVB hlwxoM97dG1omHPWV+gRZazI1nRd0yf41A+4I1RtAxhzqwwRIw9YStJA4HuRzl2i71SML+tQmKE UsNyB9CAlOf+o4QEX0Q== X-Proofpoint-GUID: 154_tEb776R1k3oHYgUoz2qjThyD5yUu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-23_05,2026-03-23_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 adultscore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 suspectscore=0 priorityscore=1501 bulkscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603230152 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: rob.clark@oss.qualcomm.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Mon, Mar 23, 2026 at 1:13=E2=80=AFPM Akhil P Oommen wrote: > > Adreno X2-85 series present in Glymur chipset supports a new mechanism > for SKU detection. A new CX_MISC register exposes the combined (or > final) speedbin value from both HW fuse register and the Soft Fuse > register. > > Implement this new SKU detection along with a new quirk to identify the > GPUs that has SOFT SKU support. Also, enable this quirk for Adreno X2-85 > and add its SKU table to the catalog. > > Signed-off-by: Akhil P Oommen > --- > drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 6 ++++ > drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 9 +++++- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 41 +++++++++++++++++++++= +----- > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 5 ---- > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + > drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 4 +++ > 6 files changed, 53 insertions(+), 13 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/= adreno/a5xx_gpu.c > index 79a441e91fa1..d7ed3225f635 100644 > --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > @@ -1731,6 +1731,7 @@ static struct msm_gpu *a5xx_gpu_init(struct drm_dev= ice *dev) > struct adreno_gpu *adreno_gpu; > struct msm_gpu *gpu; > unsigned int nr_rings; > + u32 speedbin; > int ret; > > a5xx_gpu =3D kzalloc(sizeof(*a5xx_gpu), GFP_KERNEL); > @@ -1757,6 +1758,11 @@ static struct msm_gpu *a5xx_gpu_init(struct drm_de= vice *dev) > return ERR_PTR(ret); > } > > + /* Set the speedbin value that is passed to userspace */ > + if (adreno_read_speedbin(&pdev->dev, &speedbin) || !speedbin) > + speedbin =3D 0xffff; > + adreno_gpu->speedbin =3D (uint16_t) (0xffff & speedbin); > + I will confess to not expecting to see a5xx changes in a patch adding x2-85 sku detection :-) Maybe split the code-motion out of adreno_gpu_init() into it's own commit? BR, -R > msm_mmu_set_fault_handler(to_msm_vm(gpu->vm)->mmu, gpu, > a5xx_fault_handler); > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/= msm/adreno/a6xx_catalog.c > index f6b9792531a6..758bc7bd31f6 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > @@ -1902,7 +1902,8 @@ static const struct adreno_info a8xx_gpus[] =3D { > .gmem =3D 21 * SZ_1M, > .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, > .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | > - ADRENO_QUIRK_HAS_HW_APRIV, > + ADRENO_QUIRK_HAS_HW_APRIV | > + ADRENO_QUIRK_SOFTFUSE, > .funcs =3D &a8xx_gpu_funcs, > .a6xx =3D &(const struct a6xx_info) { > .protect =3D &x285_protect, > @@ -1922,6 +1923,12 @@ static const struct adreno_info a8xx_gpus[] =3D { > { /* sentinel */ }, > }, > }, > + .speedbins =3D ADRENO_SPEEDBINS( > + { 0, 0 }, > + { 388, 1 }, > + { 357, 2 }, > + { 284, 3 }, > + ), > }, { > .chip_ids =3D ADRENO_CHIP_IDS(0x44050a01), > .family =3D ADRENO_8XX_GEN2, > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/= adreno/a6xx_gpu.c > index cbc803d90673..0fe6d803e628 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -2552,13 +2552,33 @@ static u32 fuse_to_supp_hw(const struct adreno_in= fo *info, u32 fuse) > return UINT_MAX; > } > > -static int a6xx_set_supported_hw(struct device *dev, const struct adreno= _info *info) > +static int a6xx_read_speedbin(struct device *dev, struct a6xx_gpu *a6xx_= gpu, > + const struct adreno_info *info, u32 *speedbin) > +{ > + int ret; > + > + /* Use speedbin fuse if present. Otherwise, fallback to softfuse = */ > + ret =3D adreno_read_speedbin(dev, speedbin); > + if (ret !=3D -ENOENT) > + return ret; > + > + if (info->quirks & ADRENO_QUIRK_SOFTFUSE) { > + *speedbin =3D a6xx_llc_read(a6xx_gpu, REG_A8XX_CX_MISC_SW= _FUSE_FREQ_LIMIT_STATUS); > + *speedbin =3D A8XX_CX_MISC_SW_FUSE_FREQ_LIMIT_STATUS_FINA= LFREQLIMIT(*speedbin); > + return 0; > + } > + > + return -ENOENT; > +} > + > +static int a6xx_set_supported_hw(struct device *dev, struct a6xx_gpu *a6= xx_gpu, > + const struct adreno_info *info) > { > u32 supp_hw; > u32 speedbin; > int ret; > > - ret =3D adreno_read_speedbin(dev, &speedbin); > + ret =3D a6xx_read_speedbin(dev, a6xx_gpu, info, &speedbin); > /* > * -ENOENT means that the platform doesn't support speedbin which= is > * fine > @@ -2592,11 +2612,13 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_d= evice *dev) > struct msm_drm_private *priv =3D dev->dev_private; > struct platform_device *pdev =3D priv->gpu_pdev; > struct adreno_platform_config *config =3D pdev->dev.platform_data= ; > + const struct adreno_info *info =3D config->info; > struct device_node *node; > struct a6xx_gpu *a6xx_gpu; > struct adreno_gpu *adreno_gpu; > struct msm_gpu *gpu; > extern int enable_preemption; > + u32 speedbin; > bool is_a7xx; > int ret, nr_rings =3D 1; > > @@ -2619,14 +2641,14 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_d= evice *dev) > adreno_gpu->gmu_is_wrapper =3D of_device_is_compatible(node, "qco= m,adreno-gmu-wrapper"); > > adreno_gpu->base.hw_apriv =3D > - !!(config->info->quirks & ADRENO_QUIRK_HAS_HW_APRIV); > + !!(info->quirks & ADRENO_QUIRK_HAS_HW_APRIV); > > /* gpu->info only gets assigned in adreno_gpu_init(). A8x is incl= uded intentionally */ > - is_a7xx =3D config->info->family >=3D ADRENO_7XX_GEN1; > + is_a7xx =3D info->family >=3D ADRENO_7XX_GEN1; > > a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); > > - ret =3D a6xx_set_supported_hw(&pdev->dev, config->info); > + ret =3D a6xx_set_supported_hw(&pdev->dev, a6xx_gpu, info); > if (ret) { > a6xx_llc_slices_destroy(a6xx_gpu); > kfree(a6xx_gpu); > @@ -2634,15 +2656,20 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_d= evice *dev) > } > > if ((enable_preemption =3D=3D 1) || (enable_preemption =3D=3D -1 = && > - (config->info->quirks & ADRENO_QUIRK_PREEMPTION))) > + (info->quirks & ADRENO_QUIRK_PREEMPTION))) > nr_rings =3D 4; > > - ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, config->info->func= s, nr_rings); > + ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, info->funcs, nr_ri= ngs); > if (ret) { > a6xx_destroy(&(a6xx_gpu->base.base)); > return ERR_PTR(ret); > } > > + /* Set the speedbin value that is passed to userspace */ > + if (a6xx_read_speedbin(&pdev->dev, a6xx_gpu, info, &speedbin) || = !speedbin) > + speedbin =3D 0xffff; > + adreno_gpu->speedbin =3D (uint16_t) (0xffff & speedbin); > + > /* > * For now only clamp to idle freq for devices where this is know= n not > * to cause power supply issues: > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/ms= m/adreno/adreno_gpu.c > index 10d9e5f40640..826661cb7988 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c > @@ -1184,7 +1184,6 @@ int adreno_gpu_init(struct drm_device *drm, struct = platform_device *pdev, > struct msm_gpu_config adreno_gpu_config =3D { 0 }; > struct msm_gpu *gpu =3D &adreno_gpu->base; > const char *gpu_name; > - u32 speedbin; > int ret; > > adreno_gpu->funcs =3D funcs; > @@ -1213,10 +1212,6 @@ int adreno_gpu_init(struct drm_device *drm, struct= platform_device *pdev, > devm_pm_opp_set_clkname(dev, "core"); > } > > - if (adreno_read_speedbin(dev, &speedbin) || !speedbin) > - speedbin =3D 0xffff; > - adreno_gpu->speedbin =3D (uint16_t) (0xffff & speedbin); > - > gpu_name =3D devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT= , > ADRENO_CHIPID_ARGS(config->chip_id)); > if (!gpu_name) > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/ms= m/adreno/adreno_gpu.h > index 29097e6b4253..044ed4d49aa7 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > @@ -63,6 +63,7 @@ enum adreno_family { > #define ADRENO_QUIRK_PREEMPTION BIT(5) > #define ADRENO_QUIRK_4GB_VA BIT(6) > #define ADRENO_QUIRK_IFPC BIT(7) > +#define ADRENO_QUIRK_SOFTFUSE BIT(8) > > /* Helper for formating the chip_id in the way that userspace tools like > * crashdec expect. > diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml b/drivers/gpu/= drm/msm/registers/adreno/a6xx.xml > index 3941e7510754..2309870f5031 100644 > --- a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml > +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml > @@ -5016,6 +5016,10 @@ by a particular renderpass/blit. > > > > + > + > + > + > > > > > -- > 2.51.0 >