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[209.85.221.170]) by smtp.gmail.com with ESMTPSA id a1e0cc1a2514c-95fc2f874easm692733241.9.2026.05.15.01.47.58 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 15 May 2026 01:47:58 -0700 (PDT) Received: by mail-vk1-f170.google.com with SMTP id 71dfb90a1353d-57513ac61f0so2673044e0c.3 for ; Fri, 15 May 2026 01:47:58 -0700 (PDT) X-Forwarded-Encrypted: i=1; AFNElJ+LTjrI2x2+8GG3MOkfrvUminzMf9Ymknvt8VGR6/CLyf/tBqz33WlSQeNGMdCbhPUYggC3DNHo7J8=@lists.freedesktop.org X-Received: by 2002:a05:6102:358e:b0:62f:34db:9474 with SMTP id ada2fe7eead31-63a3ee86884mr1297663137.20.1778834878086; Fri, 15 May 2026 01:47:58 -0700 (PDT) MIME-Version: 1.0 References: <20260514-rcar-du-dsc-v1-0-d65f7a9e9841@ideasonboard.com> <20260514-rcar-du-dsc-v1-3-d65f7a9e9841@ideasonboard.com> <6db159d9-56af-4d79-a1f1-9d5a6349b5ac@ideasonboard.com> In-Reply-To: From: Geert Uytterhoeven Date: Fri, 15 May 2026 10:47:46 +0200 X-Gmail-Original-Message-ID: X-Gm-Features: AVHnY4JCOAjr3bsj3LmrYGms2JUgvp1AhIShwYqx91e-BUfZ61J5zvr2A9mA72E Message-ID: Subject: Re: [PATCH 3/5] drm/rcar-du: dsc: Add rudimentary Renesas R-Car V4H DSC driver To: Tomi Valkeinen Cc: Michael Turquette , Stephen Boyd , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Marek Vasut , Laurent Pinchart , Kieran Bingham , Philipp Zabel , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Content-Type: text/plain; charset="UTF-8" X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi Tomi, On Fri, 15 May 2026 at 10:17, Tomi Valkeinen wrote: > On 15/05/2026 11:05, Geert Uytterhoeven wrote: > > On Fri, 15 May 2026 at 10:03, Tomi Valkeinen > > wrote: > >> On 15/05/2026 10:49, Geert Uytterhoeven wrote: > >>> On Thu, 14 May 2026 at 14:25, Tomi Valkeinen > >>> wrote: > >>>> From: Marek Vasut > >>>> > >>>> The Renesas DSC Display Stream Compression is a bridge embedded in the > >>>> Renesas R-Car V4H SoC. The bridge performs VESA DSC encoding of up to > >>>> 8k or 400 Mpixel/s . Add rudimentary driver, which currently acts as a > >>>> pass-through bridge and allows DSI1 to be operational on R-Car V4H. > >>>> > >>>> Signed-off-by: Marek Vasut > >>>> [tomi.valkeinen: use bridge->next_bridge, minor changes] > >>>> Signed-off-by: Tomi Valkeinen > >>> > >>> Thanks for your patch! > >>> > >>>> --- /dev/null > >>>> +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_dsc.c > >>> > >>>> + > >>>> +static void rcar_dsc_atomic_enable(struct drm_bridge *bridge, > >>>> + struct drm_atomic_state *state) > >>>> +{ > >>>> + struct rcar_dsc *dsc = bridge_to_rcar_dsc(bridge); > >>>> + > >>>> + WARN_ON(clk_prepare_enable(dsc->clk)); > >> > >> Ah, just missed your comment and sent the v2. > >> > >>> Who don't you use pm_runtime_resume_and_get() instead, like > >>> rcar_cmm.c? Then you don't need to get the clock at all, and the driver > >> > >> Hmm, why wouldn't I need to get the clock? What does the runtime PM do > >> on Renesas? > > > > Runtime PM powers on the power domain (if present), and starts > > the device by enabling its module clock. > > > >>> will keep on working if the DSC ever ends up in a power domain. > >> I can add runtime PM. I just felt that it was overcomplicating a "dummy" > >> driver that just needs to enable the clock when the video pipeline is > >> enabled. > > > > Funny, I would say you are overcomplicating a dummy driver by adding > > explicit clock control ;-) > Well, now that I know the runtime PM does magics behind the scenes, you > are right =). > > How's "module clock" defined? Is it the first clock in the clocks DT > property? It's the clock pointing to the cpg device node, and having "CPG_MOD" as its first cell. Usually it's the first clock. Note that e.g. the DU is special, as it' is represented by a single device node with multiple module clocks (and multiple (but less) resets), due to the tight integration between the individual channels. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds