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[209.85.222.172]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8d2a8740491sm1536447985a.38.2026.04.08.06.26.42 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 08 Apr 2026 06:26:42 -0700 (PDT) Received: by mail-qk1-f172.google.com with SMTP id af79cd13be357-8cbc593a67aso626721685a.2 for ; Wed, 08 Apr 2026 06:26:42 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCVd6P76TnC0AZS2zq+GGJfYG9AeMLqX+C1O0KQ9eEQe+aNxjLYSeusxCwZhJdZOiibqrZDnhV6PXI8=@lists.freedesktop.org X-Received: by 2002:a05:6122:4b05:b0:56d:3b69:87d2 with SMTP id 71dfb90a1353d-56dab9df26emr8767911e0c.11.1775654366102; Wed, 08 Apr 2026 06:19:26 -0700 (PDT) MIME-Version: 1.0 References: <24d3853ca2522df21e6a071a23e23ba4ca4b7276.1775636898.git.tommaso.merciai.xr@bp.renesas.com> In-Reply-To: <24d3853ca2522df21e6a071a23e23ba4ca4b7276.1775636898.git.tommaso.merciai.xr@bp.renesas.com> From: Geert Uytterhoeven Date: Wed, 8 Apr 2026 15:19:14 +0200 X-Gmail-Original-Message-ID: X-Gm-Features: AQROBzC36oVu26dy7QAue_JJJeRvfbuifO9CcFeX81T2keIzqU6JIH81ayIbX9M Message-ID: Subject: Re: [PATCH v6 01/21] clk: renesas: rzv2h: Add PLLDSI clk mux support To: Tommaso Merciai Cc: tomm.merciai@gmail.com, laurent.pinchart@ideasonboard.com, linux-renesas-soc@vger.kernel.org, biju.das.jz@bp.renesas.com, Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Magnus Damm , Laurent Pinchart , Tomi Valkeinen , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Content-Type: text/plain; charset="UTF-8" X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Wed, 8 Apr 2026 at 12:38, Tommaso Merciai wrote: > Add PLLDSI clk mux support to select PLLDSI clock from different clock > sources. > > Introduce the DEF_PLLDSI_SMUX() macro to define these muxes and register > them in the clock driver. > > Extend the determine_rate callback to calculate and propagate PLL > parameters via rzv2h_get_pll_dtable_pars() when LVDS output is selected, > using a new helper function rzv2h_cpg_plldsi_smux_lvds_determine_rate(). > > The CLK_SMUX2_DSI{0,1}_CLK clock multiplexers select between two paths > with different duty cycles: > > - CDIV7_DSIx_CLK (LVDS path, parent index 0): asymmetric H/L=4/3 duty (4/7) > - CSDIV_DSIx (DSI/RGB path, parent index 1): symmetric 50% duty (1/2) > > Implement rzv2h_cpg_plldsi_smux_{get,set}_duty_cycle clock operations to > allow the DRM driver to query and configure the appropriate clock path > based on the required output duty cycle. > > Signed-off-by: Tommaso Merciai > --- > v5->v6: > - Fixed rzv2h_cpg_plldsi_smux_clk_register() removed u8 width, mask > variables and replaced with direct use of smux.width and clk_div_mask(smux.width). Reviewed-by: Geert Uytterhoeven Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds