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[209.85.160.180]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-50d4b93dd05sm162222621cf.9.2026.04.08.06.29.17 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 08 Apr 2026 06:29:17 -0700 (PDT) Received: by mail-qt1-f180.google.com with SMTP id d75a77b69052e-50b392f1846so87383991cf.3 for ; Wed, 08 Apr 2026 06:29:17 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCV5/jx3sj3aUyy/u3W8Lney3HNom3f9QbV1DpAvsWLsew9Qt8nmVf5C1PjD5s/XZjrDm36jhU0+uzM=@lists.freedesktop.org X-Received: by 2002:a05:6122:3a03:b0:56f:1a26:563a with SMTP id 71dfb90a1353d-56f1a265761mr1211064e0c.7.1775654605828; Wed, 08 Apr 2026 06:23:25 -0700 (PDT) MIME-Version: 1.0 References: <9595f56ce8ab120477bfc11eaafb0f2b655d049a.1775636898.git.tommaso.merciai.xr@bp.renesas.com> In-Reply-To: <9595f56ce8ab120477bfc11eaafb0f2b655d049a.1775636898.git.tommaso.merciai.xr@bp.renesas.com> From: Geert Uytterhoeven Date: Wed, 8 Apr 2026 15:23:14 +0200 X-Gmail-Original-Message-ID: X-Gm-Features: AQROBzCAS3tdwS4I5i1ony0ZYqV2Tos82DINalsSZpND3OxFU3AJc31boq9f15A Message-ID: Subject: Re: [PATCH v6 06/21] clk: renesas: r9a09g047: Add support for SMUX2_DSI{0, 1}_CLK To: Tommaso Merciai Cc: tomm.merciai@gmail.com, laurent.pinchart@ideasonboard.com, linux-renesas-soc@vger.kernel.org, biju.das.jz@bp.renesas.com, Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Magnus Damm , Laurent Pinchart , Tomi Valkeinen , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Content-Type: text/plain; charset="UTF-8" X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Wed, 8 Apr 2026 at 12:38, Tommaso Merciai wrote: > Add support for the SMUX2_DSI0_CLK and SMUX2_DSI1_CLK clock muxes > present on the r9a09g047 SoC. > > These muxes select between CDIV7_DSI{0,1}_CLK and CSDIV_2to16_PLLDSI{0,1} > using the CPG_SSEL3 register (SELCTL0 and SELCTL1 bits). > > According to the hardware manual, when LVDS0 or LVDS1 outputs are used, > SELCTL0 or SELCTL1 must be set accordingly. > > Signed-off-by: Tommaso Merciai Reviewed-by: Geert Uytterhoeven Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds