Re: [PATCH] drm/i915/color: Fix plane color pipeline programming bugs

[Sean Paul <seanpaul@google.com>]

On Thu, May 21, 2026 at 2:39 PM Jani Nikula <jani.nikula@linux.intel.com> wrote:
>
> On Thu, 21 May 2026, Sean Paul <sean@poorly.run> wrote:
> > From: Sean Paul <seanpaul@google.com>
> >
> > Fix two bugs in the plane-level color pipeline programming:
> > 1. Fix a step discontinuity in the Post-CSC Gamma LUT when SDR dimming
> >    is active by clamping Segment 2 to the last user-provided LUT entry
> >    value instead of hardcoding it to 1.0 (1 << 24).
> > 2. Fix a typo in the loop condition in xelpd_program_plane_pre_csc_lut
> >    for Segment 2 degamma programming, changing 'while (i++ > 130)' to
> >    'while (i++ < 130)'. Also clamp Segment 2 to the last user-provided
> >    LUT entry value instead of hardcoding it to 1.0 (1 << 24) to fix
> >    a step discontinuity similar to the Post-CSC fix.
>
> One fix per patch, please.

Ack

>
> For #2 there's already [1].

This isn't in drm-tip or drm-intel afaict. I'll drop it out of my set,
but could you please apply it?

Sean

>
> BR,
> Jani.
>
> [1] https://lore.kernel.org/r/20260519075245.383864-1-pranay.samala@intel.com
>
> >
> > Signed-off-by: Sean Paul <seanpaul@google.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_color.c | 11 ++++++-----
> >  1 file changed, 6 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> > index 2d318e922671..9b807b024ec3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_color.c
> > +++ b/drivers/gpu/drm/i915/display/intel_color.c
> > @@ -3953,6 +3953,7 @@ xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb,
> >       enum plane_id plane = to_intel_plane(state->plane)->id;
> >       const struct drm_color_lut32 *pre_csc_lut = plane_state->hw.degamma_lut->data;
> >       u32 i, lut_size;
> > +     u32 lut_val = 1 << 24;
> >
> >       if (icl_is_hdr_plane(display, plane)) {
> >               lut_size = 128;
> > @@ -3963,7 +3964,7 @@ xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb,
> >
> >               if (pre_csc_lut) {
> >                       for (i = 0; i < lut_size; i++) {
> > -                             u32 lut_val = drm_color_lut32_extract(pre_csc_lut[i].green, 24);
> > +                             lut_val = drm_color_lut32_extract(pre_csc_lut[i].green, 24);
> >
> >                               intel_de_write_dsb(display, dsb,
> >                                                  PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
> > @@ -3975,8 +3976,8 @@ xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb,
> >                       do {
> >                               intel_de_write_dsb(display, dsb,
> >                                                  PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
> > -                                                (1 << 24));
> > -                     } while (i++ > 130);
> > +                                                lut_val);
> > +                     } while (i++ < 130);
> >               } else {
> >                       for (i = 0; i < lut_size; i++) {
> >                               u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1);
> > @@ -4023,11 +4024,11 @@ xelpd_program_plane_post_csc_lut(struct intel_dsb *dsb,
> >                                                  lut_val);
> >                       }
> >
> > -                     /* Segment 2 */
> > +                     /* Segment 2 - clamp to the last LUT value to prevent step discontinuity */
> >                       do {
> >                               intel_de_write_dsb(display, dsb,
> >                                                  PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0),
> > -                                                (1 << 24));
> > +                                                lut_val);
> >                       } while (i++ < 34);
> >               } else {
> >                       /*TODO: Add for segment 0 */
>
> --
> Jani Nikula, Intel