From: "Cavitt, Jonathan" <jonathan.cavitt@intel.com>
To: "Almahallawy, Khaled" <khaled.almahallawy@intel.com>,
"dri-devel@lists.freedesktop.org"
<dri-devel@lists.freedesktop.org>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>,
"intel-xe@lists.freedesktop.org" <intel-xe@lists.freedesktop.org>
Cc: "Shankar, Uma" <uma.shankar@intel.com>,
Sean Paul <seanpaul@chromium.org>,
"Nikula, Jani" <jani.nikula@intel.com>,
"Cavitt, Jonathan" <jonathan.cavitt@intel.com>
Subject: RE: [PATCH] drm/display: Increase DP_RECEIVER_CAP_SIZE from 15 to 16 bytes
Date: Mon, 7 Jul 2025 13:51:27 +0000 [thread overview]
Message-ID: <CH0PR11MB54448C1EA1427095093C0117E54FA@CH0PR11MB5444.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20250702223903.3801654-1-khaled.almahallawy@intel.com>
-----Original Message-----
From: Almahallawy, Khaled <khaled.almahallawy@intel.com>
Sent: Wednesday, July 2, 2025 3:39 PM
To: dri-devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
Cc: Almahallawy, Khaled <khaled.almahallawy@intel.com>; Shankar, Uma <uma.shankar@intel.com>; Sean Paul <seanpaul@chromium.org>; Cavitt, Jonathan <jonathan.cavitt@intel.com>; Nikula, Jani <jani.nikula@intel.com>
Subject: [PATCH] drm/display: Increase DP_RECEIVER_CAP_SIZE from 15 to 16 bytes
>
> Several Link Layer tests (4.2.2.1-2, 4.2.2.7-9) fail because DPTX doesn't
> read DPCD ADAPTER_CAP addresses (0x000F and 0x220F).
>
> 4.2.2.1 test states [1]:
> "Fail1: Source DUT failed to read the DPCD Receiver Capability field
> (DPCD:00000h:0000Fh) through AUX_CH before link training."
>
> 4.2.2.2 test states [1]:
> "Fail2: Source DUT failed to read the DPCD Extended Receiver Capability
> field (DPCD:02200h:0220Fh) through AUX_CH before link training."
>
> Additionally, the spec [2] states:
> "The Source device shall respond to Hot Plug event/Hot Re-plug event by
> first reading DPCD Link/Sink Device Status registers at DPCD 00200h
> through 00205h -or- DPCD 02002h through 0200Fh. If the link is unstable
> or lost, the Source device then reads the DPCD Receiver Capabilities
> registers at DPCD 00000h through 0000Fh to determine the appropriate
> information needed to train the link. The Source device shall then
> initiate link training."
>
> Increasing DP_RECEIVER_CAP_SIZE by 1 byte ensures passing the test
> conditions for these link layer tests.
>
> [1]: DisplayPort v2.1 Link Layer Compliance Test Specification
> sections 4.2.2.1 & 4.2.2.2
> [2]: DisplayPort Standard v2.1 - Sec 5.1.4 Source Device Behavior
> upon HPD Pulse Detection
>
> Cc: Uma Shankar <uma.shankar@intel.com>
> Cc: Sean Paul <seanpaul@chromium.org>
> Cc: Jonathan Cavitt <jonathan.cavitt@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com>
LGTM.
Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
-Jonathan Cavitt
> ---
> include/drm/display/drm_dp.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
> index 811e9238a77c..960c9757ba76 100644
> --- a/include/drm/display/drm_dp.h
> +++ b/include/drm/display/drm_dp.h
> @@ -1681,7 +1681,7 @@ enum drm_dp_phy {
> #define DP_LINK_STATUS_SIZE 6
>
> #define DP_BRANCH_OUI_HEADER_SIZE 0xc
> -#define DP_RECEIVER_CAP_SIZE 0xf
> +#define DP_RECEIVER_CAP_SIZE 0x10
> #define DP_DSC_RECEIVER_CAP_SIZE 0x10 /* DSC Capabilities 0x60 through 0x6F */
> #define EDP_PSR_RECEIVER_CAP_SIZE 2
> #define EDP_DISPLAY_CTL_CAP_SIZE 5
> --
> 2.43.0
>
>
next prev parent reply other threads:[~2025-07-07 13:51 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-02 22:39 [PATCH] drm/display: Increase DP_RECEIVER_CAP_SIZE from 15 to 16 bytes Khaled Almahallawy
2025-07-07 13:51 ` Cavitt, Jonathan [this message]
2026-03-13 5:00 ` [PATCH v2] " Khaled Almahallawy
2026-03-13 21:29 ` Claude review: " Claude Code Review Bot
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