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Sat, 21 Mar 2026 16:50:38 +0000 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Sat, 21 Mar 2026 16:50:38 +0000 Message-Id: Cc: , , , , Subject: Re: [PATCH v2 8/8] gpu: nova-core: convert to new dma::Coherent API From: "Gary Guo" To: "Danilo Krummrich" , , , , , , , , , , , , X-Mailer: aerc 0.21.0 References: <20260320194626.36263-1-dakr@kernel.org> <20260320194626.36263-9-dakr@kernel.org> In-Reply-To: <20260320194626.36263-9-dakr@kernel.org> X-ClientProxiedBy: LO4P265CA0088.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:2bc::7) To LOVP265MB8871.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:488::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LOVP265MB8871:EE_|LO0P265MB6131:EE_ X-MS-Office365-Filtering-Correlation-Id: d081c355-dd89-42f0-d18c-08de8769fb06 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|7416014|1800799024|366016|10070799003|921020|7053199007|18002099003|22082099003|56012099003; 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Hi Danilo, It looks like with Alex's "gpu: nova-core: create falcon firmware DMA objec= ts lazily" landed, all others users of the old API are now gone. So this line could be dropped and `impl CoherentAllocation` and the type al= ias can be removed after this patch. Best, Gary > > Signed-off-by: Gary Guo > Co-developed-by: Danilo Krummrich > Signed-off-by: Danilo Krummrich > --- > drivers/gpu/nova-core/dma.rs | 19 ++++++------- > drivers/gpu/nova-core/falcon.rs | 5 ++-- > drivers/gpu/nova-core/gsp.rs | 21 ++++++++------ > drivers/gpu/nova-core/gsp/cmdq.rs | 21 ++++++-------- > drivers/gpu/nova-core/gsp/fw.rs | 46 ++++++++++--------------------- > 5 files changed, 47 insertions(+), 65 deletions(-) > > diff --git a/drivers/gpu/nova-core/dma.rs b/drivers/gpu/nova-core/dma.rs > index 7215398969da..3c19d5ffcfe8 100644 > --- a/drivers/gpu/nova-core/dma.rs > +++ b/drivers/gpu/nova-core/dma.rs > @@ -9,13 +9,13 @@ > =20 > use kernel::{ > device, > - dma::CoherentAllocation, > + dma::Coherent, > page::PAGE_SIZE, > prelude::*, // > }; > =20 > pub(crate) struct DmaObject { > - dma: CoherentAllocation, > + dma: Coherent<[u8]>, > } > =20 > impl DmaObject { > @@ -24,23 +24,22 @@ pub(crate) fn new(dev: &device::Device= , len: usize) -> Result .map_err(|_| EINVAL)? > .pad_to_align() > .size(); > - let dma =3D CoherentAllocation::alloc_coherent(dev, len, GFP_KER= NEL | __GFP_ZERO)?; > + let dma =3D Coherent::zeroed_slice(dev, len, GFP_KERNEL)?; > =20 > Ok(Self { dma }) > } > =20 > pub(crate) fn from_data(dev: &device::Device, data: &= [u8]) -> Result { > - Self::new(dev, data.len()).and_then(|mut dma_obj| { > - // SAFETY: We have just allocated the DMA memory, we are the= only users and > - // we haven't made the device aware of the handle yet. > - unsafe { dma_obj.write(data, 0)? } > - Ok(dma_obj) > - }) > + let dma_obj =3D Self::new(dev, data.len())?; > + // SAFETY: We have just allocated the DMA memory, we are the onl= y users and > + // we haven't made the device aware of the handle yet. > + unsafe { dma_obj.as_mut()[..data.len()].copy_from_slice(data) }; > + Ok(dma_obj) > } > } > =20 > impl Deref for DmaObject { > - type Target =3D CoherentAllocation; > + type Target =3D Coherent<[u8]>; > =20 > fn deref(&self) -> &Self::Target { > &self.dma > diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falc= on.rs > index 7097a206ec3c..5bf8da8760bf 100644 > --- a/drivers/gpu/nova-core/falcon.rs > +++ b/drivers/gpu/nova-core/falcon.rs > @@ -26,8 +26,7 @@ > gpu::Chipset, > num::{ > self, > - FromSafeCast, > - IntoSafeCast, // > + FromSafeCast, // > }, > regs, > regs::macros::RegisterBase, // > @@ -653,7 +652,7 @@ fn dma_wr( > } > FalconMem::Dmem =3D> ( > 0, > - dma_obj.dma_handle_with_offset(load_offsets.src_start.in= to_safe_cast())?, > + dma_obj.dma_handle() + DmaAddress::from(load_offsets.src= _start), > ), > }; > if dma_start % DmaAddress::from(DMA_LEN) > 0 { > diff --git a/drivers/gpu/nova-core/gsp.rs b/drivers/gpu/nova-core/gsp.rs > index f0a50bdc4c00..a045c4189989 100644 > --- a/drivers/gpu/nova-core/gsp.rs > +++ b/drivers/gpu/nova-core/gsp.rs > @@ -6,13 +6,15 @@ > device, > dma::{ > Coherent, > - CoherentAllocation, > CoherentBox, > DmaAddress, // > }, > pci, > prelude::*, > - transmute::AsBytes, // > + transmute::{ > + AsBytes, > + FromBytes, // > + }, // > }; > =20 > pub(crate) mod cmdq; > @@ -44,6 +46,9 @@ > #[repr(C)] > struct PteArray([u64; NUM_ENTRIES]); > =20 > +/// SAFETY: arrays of `u64` implement `FromBytes` and we are but a wrapp= er around one. > +unsafe impl FromBytes for PteArray {} > + > /// SAFETY: arrays of `u64` implement `AsBytes` and we are but a wrapper= around one. > unsafe impl AsBytes for PteArray = {} > =20 > @@ -71,26 +76,24 @@ fn entry(start: DmaAddress, index: usize) -> Result { > /// then pp points to index into the buffer where the next logging entry= will > /// be written. Therefore, the logging data is valid if: > /// 1 <=3D pp < sizeof(buffer)/sizeof(u64) > -struct LogBuffer(CoherentAllocation); > +struct LogBuffer(Coherent<[u8]>); > =20 > impl LogBuffer { > /// Creates a new `LogBuffer` mapped on `dev`. > fn new(dev: &device::Device) -> Result { > const NUM_PAGES: usize =3D RM_LOG_BUFFER_NUM_PAGES; > =20 > - let mut obj =3D Self(CoherentAllocation::::alloc_coherent( > + let obj =3D Self(Coherent::::zeroed_slice( > dev, > NUM_PAGES * GSP_PAGE_SIZE, > - GFP_KERNEL | __GFP_ZERO, > + GFP_KERNEL, > )?); > =20 > let start_addr =3D obj.0.dma_handle(); > =20 > // SAFETY: `obj` has just been created and we are its sole user. > - let pte_region =3D unsafe { > - obj.0 > - .as_slice_mut(size_of::(), NUM_PAGES * size_of::())? > - }; > + let pte_region =3D > + unsafe { &mut obj.0.as_mut()[size_of::()..][..NUM_PAGES= * size_of::()] }; > =20 > // Write values one by one to avoid an on-stack instance of `Pte= Array`. > for (i, chunk) in pte_region.chunks_exact_mut(size_of::()).= enumerate() { > diff --git a/drivers/gpu/nova-core/gsp/cmdq.rs b/drivers/gpu/nova-core/gs= p/cmdq.rs > index d36a62ba1c60..f38790601a0f 100644 > --- a/drivers/gpu/nova-core/gsp/cmdq.rs > +++ b/drivers/gpu/nova-core/gsp/cmdq.rs > @@ -7,7 +7,7 @@ > use kernel::{ > device, > dma::{ > - CoherentAllocation, > + Coherent, > DmaAddress, // > }, > dma_write, > @@ -207,7 +207,7 @@ unsafe impl AsBytes for GspMem {} > // that is not a problem because they are not used outside the kernel. > unsafe impl FromBytes for GspMem {} > =20 > -/// Wrapper around [`GspMem`] to share it with the GPU using a [`Coheren= tAllocation`]. > +/// Wrapper around [`GspMem`] to share it with the GPU using a [`Coheren= t`]. > /// > /// This provides the low-level functionality to communicate with the GS= P, including allocation of > /// queue space to write messages to and management of read/write pointe= rs. > @@ -218,7 +218,7 @@ unsafe impl FromBytes for GspMem {} > /// pointer and the GSP read pointer. This region is returned by [`Sel= f::driver_write_area`]. > /// * The driver owns (i.e. can read from) the part of the GSP message q= ueue between the CPU read > /// pointer and the GSP write pointer. This region is returned by [`Se= lf::driver_read_area`]. > -struct DmaGspMem(CoherentAllocation); > +struct DmaGspMem(Coherent); > =20 > impl DmaGspMem { > /// Allocate a new instance and map it for `dev`. > @@ -226,21 +226,20 @@ fn new(dev: &device::Device) -> Resu= lt { > const MSGQ_SIZE: u32 =3D num::usize_into_u32::<{ size_of::= () }>(); > const RX_HDR_OFF: u32 =3D num::usize_into_u32::<{ mem::offset_of= !(Msgq, rx) }>(); > =20 > - let gsp_mem =3D > - CoherentAllocation::::alloc_coherent(dev, 1, GFP_KER= NEL | __GFP_ZERO)?; > + let gsp_mem =3D Coherent::::zeroed(dev, GFP_KERNEL)?; > =20 > let start =3D gsp_mem.dma_handle(); > // Write values one by one to avoid an on-stack instance of `Pte= Array`. > for i in 0..GspMem::PTE_ARRAY_SIZE { > - dma_write!(gsp_mem, [0]?.ptes.0[i], PteArray::<0>::entry(sta= rt, i)?); > + dma_write!(gsp_mem, .ptes.0[i], PteArray::<0>::entry(start, = i)?); > } > =20 > dma_write!( > gsp_mem, > - [0]?.cpuq.tx, > + .cpuq.tx, > MsgqTxHeader::new(MSGQ_SIZE, RX_HDR_OFF, MSGQ_NUM_PAGES) > ); > - dma_write!(gsp_mem, [0]?.cpuq.rx, MsgqRxHeader::new()); > + dma_write!(gsp_mem, .cpuq.rx, MsgqRxHeader::new()); > =20 > Ok(Self(gsp_mem)) > } > @@ -255,10 +254,9 @@ fn new(dev: &device::Device) -> Resul= t { > let rx =3D self.gsp_read_ptr() as usize; > =20 > // SAFETY: > - // - The `CoherentAllocation` contains exactly one object. > // - We will only access the driver-owned part of the shared mem= ory. > // - Per the safety statement of the function, no concurrent acc= ess will be performed. > - let gsp_mem =3D &mut unsafe { self.0.as_slice_mut(0, 1) }.unwrap= ()[0]; > + let gsp_mem =3D unsafe { &mut *self.0.as_mut() }; > // PANIC: per the invariant of `cpu_write_ptr`, `tx` is `< MSGQ_= NUM_PAGES`. > let (before_tx, after_tx) =3D gsp_mem.cpuq.msgq.data.split_at_mu= t(tx); > =20 > @@ -309,10 +307,9 @@ fn driver_write_area_size(&self) -> usize { > let rx =3D self.cpu_read_ptr() as usize; > =20 > // SAFETY: > - // - The `CoherentAllocation` contains exactly one object. > // - We will only access the driver-owned part of the shared mem= ory. > // - Per the safety statement of the function, no concurrent acc= ess will be performed. > - let gsp_mem =3D &unsafe { self.0.as_slice(0, 1) }.unwrap()[0]; > + let gsp_mem =3D unsafe { &*self.0.as_ptr() }; > let data =3D &gsp_mem.gspq.msgq.data; > =20 > // The area starting at `rx` and ending at `tx - 1` modulo MSGQ_= NUM_PAGES, inclusive, > diff --git a/drivers/gpu/nova-core/gsp/fw.rs b/drivers/gpu/nova-core/gsp/= fw.rs > index 0d8daf6a80b7..847b5eb215d4 100644 > --- a/drivers/gpu/nova-core/gsp/fw.rs > +++ b/drivers/gpu/nova-core/gsp/fw.rs > @@ -40,8 +40,7 @@ > }, > }; > =20 > -// TODO: Replace with `IoView` projections once available; the `unwrap()= ` calls go away once we > -// switch to the new `dma::Coherent` API. > +// TODO: Replace with `IoView` projections once available. > pub(super) mod gsp_mem { > use core::sync::atomic::{ > fence, > @@ -49,10 +48,9 @@ pub(super) mod gsp_mem { > }; > =20 > use kernel::{ > - dma::CoherentAllocation, > + dma::Coherent, > dma_read, > - dma_write, > - prelude::*, // > + dma_write, // > }; > =20 > use crate::gsp::cmdq::{ > @@ -60,49 +58,35 @@ pub(super) mod gsp_mem { > MSGQ_NUM_PAGES, // > }; > =20 > - pub(in crate::gsp) fn gsp_write_ptr(qs: &CoherentAllocation)= -> u32 { > - // PANIC: A `dma::CoherentAllocation` always contains at least o= ne element. > - || -> Result { Ok(dma_read!(qs, [0]?.gspq.tx.0.writePtr) % = MSGQ_NUM_PAGES) }().unwrap() > + pub(in crate::gsp) fn gsp_write_ptr(qs: &Coherent) -> u32 { > + dma_read!(qs, .gspq.tx.0.writePtr) % MSGQ_NUM_PAGES > } > =20 > - pub(in crate::gsp) fn gsp_read_ptr(qs: &CoherentAllocation) = -> u32 { > - // PANIC: A `dma::CoherentAllocation` always contains at least o= ne element. > - || -> Result { Ok(dma_read!(qs, [0]?.gspq.rx.0.readPtr) % M= SGQ_NUM_PAGES) }().unwrap() > + pub(in crate::gsp) fn gsp_read_ptr(qs: &Coherent) -> u32 { > + dma_read!(qs, .gspq.rx.0.readPtr) % MSGQ_NUM_PAGES > } > =20 > - pub(in crate::gsp) fn cpu_read_ptr(qs: &CoherentAllocation) = -> u32 { > - // PANIC: A `dma::CoherentAllocation` always contains at least o= ne element. > - || -> Result { Ok(dma_read!(qs, [0]?.cpuq.rx.0.readPtr) % M= SGQ_NUM_PAGES) }().unwrap() > + pub(in crate::gsp) fn cpu_read_ptr(qs: &Coherent) -> u32 { > + dma_read!(qs, .cpuq.rx.0.readPtr) % MSGQ_NUM_PAGES > } > =20 > - pub(in crate::gsp) fn advance_cpu_read_ptr(qs: &CoherentAllocation, count: u32) { > + pub(in crate::gsp) fn advance_cpu_read_ptr(qs: &Coherent, co= unt: u32) { > let rptr =3D cpu_read_ptr(qs).wrapping_add(count) % MSGQ_NUM_PAG= ES; > =20 > // Ensure read pointer is properly ordered. > fence(Ordering::SeqCst); > =20 > - // PANIC: A `dma::CoherentAllocation` always contains at least o= ne element. > - || -> Result { > - dma_write!(qs, [0]?.cpuq.rx.0.readPtr, rptr); > - Ok(()) > - }() > - .unwrap() > + dma_write!(qs, .cpuq.rx.0.readPtr, rptr); > } > =20 > - pub(in crate::gsp) fn cpu_write_ptr(qs: &CoherentAllocation)= -> u32 { > - // PANIC: A `dma::CoherentAllocation` always contains at least o= ne element. > - || -> Result { Ok(dma_read!(qs, [0]?.cpuq.tx.0.writePtr) % = MSGQ_NUM_PAGES) }().unwrap() > + pub(in crate::gsp) fn cpu_write_ptr(qs: &Coherent) -> u32 { > + dma_read!(qs, .cpuq.tx.0.writePtr) % MSGQ_NUM_PAGES > } > =20 > - pub(in crate::gsp) fn advance_cpu_write_ptr(qs: &CoherentAllocation<= GspMem>, count: u32) { > + pub(in crate::gsp) fn advance_cpu_write_ptr(qs: &Coherent, c= ount: u32) { > let wptr =3D cpu_write_ptr(qs).wrapping_add(count) % MSGQ_NUM_PA= GES; > =20 > - // PANIC: A `dma::CoherentAllocation` always contains at least o= ne element. > - || -> Result { > - dma_write!(qs, [0]?.cpuq.tx.0.writePtr, wptr); > - Ok(()) > - }() > - .unwrap(); > + dma_write!(qs, .cpuq.tx.0.writePtr, wptr); > =20 > // Ensure all command data is visible before triggering the GSP = read. > fence(Ordering::SeqCst);