RE: [PATCH v7 2/3] drm/i915/display: Panel Replay BW optimization for DP2.0 tunneling

["Manna, Animesh" <animesh.manna@intel.com>]

> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Thursday, March 12, 2026 12:15 PM
> To: intel-xe@lists.freedesktop.org; dri-devel@lists.freedesktop.org; Manna,
> Animesh <animesh.manna@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Murthy, Arun R <arun.r.murthy@intel.com>; Nikula, Jani
> <jani.nikula@intel.com>; Deak, Imre <imre.deak@intel.com>
> Subject: Re: [PATCH v7 2/3] drm/i915/display: Panel Replay BW optimization
> for DP2.0 tunneling
> 
> On Thu, 2026-03-12 at 10:30 +0530, Animesh Manna wrote:
> > Unused bandwidth can be used by external display agents for Panel
> > Replay enabled DP panel during idleness with link on. Enable source to
> > replace dummy data from the display with data from another agent by
> > programming TRANS_DP2_CTL [Panel Replay Tunneling Enable].
> >
> > v2:
> > - Enable pr bw optimization along with panel replay enable. [Jani]
> >
> > v3:
> > - Write TRANS_DP2_CTL once for both bw optimization and panel replay
> > enable. [Jani]
> >
> > v4:
> > - Read DPCD once in init() and store in panel_replay_caps. [Jouni]
> >
> > v5:
> > - Avoid reading DPCD for edp. [Jouni]
> > - Use drm_dp_dpcd_read_byte() and some cosmetic changes. [Jani]
> >
> > v6:
> > - Extend the corresponding interface defined in drm_dp_tunnel.c to
> > query the Panel Replay optimization capability. [Imre]
> >
> > Bspec: 68920
> > Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >  .../gpu/drm/i915/display/intel_display_regs.h |  1 +
> >  drivers/gpu/drm/i915/display/intel_psr.c      | 24
> > +++++++++++++++++--
> >  2 files changed, 23 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > index 4746e9ebd920..dada8dc27ea4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > @@ -2263,6 +2263,7 @@
> >  #define TRANS_DP2_CTL(trans)			_MMIO_TRANS(trans,
> > _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B)
> >  #define  TRANS_DP2_128B132B_CHANNEL_CODING	REG_BIT(31)
> >  #define  TRANS_DP2_PANEL_REPLAY_ENABLE		REG_BIT(30)
> > +#define  TRANS_DP2_PR_TUNNELING_ENABLE		REG_BIT(26)
> >  #define  TRANS_DP2_DEBUG_ENABLE			REG_BIT(23)
> >
> >  #define _TRANS_DP2_VFREQHIGH_A			0x600a4
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 5041a5a138d1..632527ede29f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -44,6 +44,7 @@
> >  #include "intel_dmc.h"
> >  #include "intel_dp.h"
> >  #include "intel_dp_aux.h"
> > +#include "intel_dp_tunnel.h"
> >  #include "intel_dsb.h"
> >  #include "intel_frontbuffer.h"
> >  #include "intel_hdmi.h"
> > @@ -1023,11 +1024,28 @@ static u8 frames_before_su_entry(struct
> > intel_dp *intel_dp)
> >  	return frames_before_su_entry;
> >  }
> >
> > +static bool intel_psr_allow_pr_bw_optimization(struct intel_dp
> > *intel_dp)
> > +{
> > +	struct intel_display *display = to_intel_display(intel_dp);
> > +
> > +	if (DISPLAY_VER(display) < 35)
> > +		return false;
> 
> This is not necessary if you check it already at compute config.
> 
> > +
> > +	if (!intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
> > +		return false;
> > +
> > +	if (!intel_dp_tunnel_pr_optimization_supported(intel_dp))
> > +		return false;
> 
> You should move this patch after patch 3. Then you can drop this check.
> 
> > +
> > +	return true;
> > +}
> > +
> >  static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
> >  {
> >  	struct intel_display *display = to_intel_display(intel_dp);
> >  	struct intel_psr *psr = &intel_dp->psr;
> >  	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
> > +	u32 dp2_ctl_val = TRANS_DP2_PANEL_REPLAY_ENABLE;
> >
> >  	if (intel_dp_is_edp(intel_dp) && psr->sel_update_enabled) {
> >  		u32 val = psr->su_region_et_enabled ?
> > @@ -1040,12 +1058,14 @@ static void dg2_activate_panel_replay(struct
> > intel_dp *intel_dp)
> >  			       val);
> >  	}
> >
> > +	if (!intel_dp_is_edp(intel_dp) &&
> > intel_psr_allow_pr_bw_optimization(intel_dp))
> > +		dp2_ctl_val |= TRANS_DP2_PR_TUNNELING_ENABLE;
> 
> If you do modification I commented above you could just check
> intel_dp_tunnel_bw_alloc_is_enabled here. No need to add
> intel_psr_allow_pr_bw_optimization helper.

Sure, will check on this.

Regards,
Animesh
> 
> BR,
> 
> Jouni Högander
> 
> >  		     PSR2_MAN_TRK_CTL(display, intel_dp-
> > >psr.transcoder),
> >  		     0,
> > ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME);
> >
> > -	intel_de_rmw(display, TRANS_DP2_CTL(intel_dp-
> > >psr.transcoder), 0,
> > -		     TRANS_DP2_PANEL_REPLAY_ENABLE);
> > +	intel_de_rmw(display, TRANS_DP2_CTL(intel_dp-
> > >psr.transcoder), 0, dp2_ctl_val);
> >  }
> >
> >  static void hsw_activate_psr2(struct intel_dp *intel_dp)