[PATCH] drm/amd/display: Increase DCN314 SR latency by 1us

[PATCH] drm/amd/display: Increase DCN314 SR latency by 1us

[Zhang Zhenzhe]

[Why & How]

On laptops with LPDDR5 modules, underflow can be observed.
It's unclear why it only occurs on specific desktop contents. However,
increasing enter/exit latencies by 1us seems to resolve it.

Fixes: https://gitlab.freedesktop.org/drm/amd/-/issues/5065
Signed-off-by: Zhenzhe Zhang <zhenzhe.zhang@outlook.com>
---
 .../display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c   | 16 ++++++++--------
 .../drm/amd/display/dc/dml/dcn314/dcn314_fpu.c   |  4 ++--
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
index 0cb37827a..7a910cc6d 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
@@ -450,32 +450,32 @@ static struct wm_table lpddr5_wm_table = {
 			.wm_inst = WM_A,
 			.wm_type = WM_TYPE_PSTATE_CHG,
 			.pstate_latency_us = 11.65333,
-			.sr_exit_time_us = 30.0,
-			.sr_enter_plus_exit_time_us = 32.0,
+			.sr_exit_time_us = 31.0,
+			.sr_enter_plus_exit_time_us = 33.0,
 			.valid = true,
 		},
 		{
 			.wm_inst = WM_B,
 			.wm_type = WM_TYPE_PSTATE_CHG,
 			.pstate_latency_us = 11.65333,
-			.sr_exit_time_us = 30.0,
-			.sr_enter_plus_exit_time_us = 32.0,
+			.sr_exit_time_us = 31.0,
+			.sr_enter_plus_exit_time_us = 33.0,
 			.valid = true,
 		},
 		{
 			.wm_inst = WM_C,
 			.wm_type = WM_TYPE_PSTATE_CHG,
 			.pstate_latency_us = 11.65333,
-			.sr_exit_time_us = 30.0,
-			.sr_enter_plus_exit_time_us = 32.0,
+			.sr_exit_time_us = 31.0,
+			.sr_enter_plus_exit_time_us = 33.0,
 			.valid = true,
 		},
 		{
 			.wm_inst = WM_D,
 			.wm_type = WM_TYPE_PSTATE_CHG,
 			.pstate_latency_us = 11.65333,
-			.sr_exit_time_us = 30.0,
-			.sr_enter_plus_exit_time_us = 32.0,
+			.sr_exit_time_us = 31.0,
+			.sr_enter_plus_exit_time_us = 33.0,
 			.valid = true,
 		},
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
index df9d50b9b..37c760fbb 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
@@ -148,8 +148,8 @@ static struct _vcs_dpi_soc_bounding_box_st dcn3_14_soc = {
 		},
 	},
 	.num_states = 5,
-	.sr_exit_time_us = 16.5,
-	.sr_enter_plus_exit_time_us = 18.5,
+	.sr_exit_time_us = 17.5,
+	.sr_enter_plus_exit_time_us = 19.5,
 	.sr_exit_z8_time_us = 268.0,
 	.sr_enter_plus_exit_z8_time_us = 393.0,
 	.writeback_latency_us = 12.0,
-- 
2.53.0

Claude review: drm/amd/display: Increase DCN314 SR latency by 1us

[Claude Code Review Bot]

Overall Series Review

Subject: drm/amd/display: Increase DCN314 SR latency by 1us
Author: Zhang Zhenzhe <zhenzhe.zhang@outlook.com>
Patches: 1
Reviewed: 2026-03-16T12:18:55.915158

---

This is a single-patch series that increases DCN314 self-refresh (SR) enter/exit latency values by 1μs to fix display underflow on laptops with LPDDR5 memory. The change is simple, low-risk, and targets a specific reported bug. The approach — adding margin to timing parameters — is a common and well-understood fix pattern for display underflow issues in the AMDGPU display stack.

**Concern:** The commit message says "It's unclear why it only occurs on specific desktop contents," which is honest but not fully reassuring. The fix is empirical (add 1μs of margin) rather than root-cause-driven. That said, this is typical for display watermark tuning and the values are conservative bumps.

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Generated by Claude Code Patch Reviewer

Claude review: drm/amd/display: Increase DCN314 SR latency by 1us

[Claude Code Review Bot]

Patch Review

**Correctness:** The patch consistently updates all relevant locations:

1. **`dcn314_clk_mgr.c`** — The `lpddr5_wm_table` has all four watermark entries (WM_A through WM_D) updated identically:
   - `sr_exit_time_us`: 30.0 → 31.0
   - `sr_enter_plus_exit_time_us`: 32.0 → 33.0

   This is correct — the difference between `sr_enter_plus_exit_time_us` and `sr_exit_time_us` remains 2.0μs (i.e., the enter time alone is still 2μs), which preserves the original relationship.

2. **`dcn314_fpu.c`** — The `dcn3_14_soc` bounding box is updated:
   - `sr_exit_time_us`: 16.5 → 17.5
   - `sr_enter_plus_exit_time_us`: 18.5 → 19.5

   Again, the 2μs delta between enter+exit and exit-only is preserved.

**Observations:**

- The DDR5 table (`ddr5_wm_table` at line 410) is **not** modified — only the LPDDR5 table is changed. This is consistent with the commit message stating the issue is specific to LPDDR5 modules. However, the soc bounding box values in `dcn314_fpu.c` are global (not memory-type-specific), so both DDR5 and LPDDR5 paths will see the increased latency from the FPU side. This seems intentional as a conservative safety margin, but the reviewer may want to confirm the author considered whether the FPU change could affect DDR5 configurations.

- The `Fixes:` tag references a freedesktop.org GitLab issue rather than a commit SHA. This is non-standard for the kernel — typically a `Fixes:` tag references a commit that introduced the bug (format: `Fixes: <sha1> ("commit subject")`). If this is intended for stable backports, a proper `Fixes:` tag with a commit hash would be needed. If the issue just tracks the bug report, consider using `Link:` or `Closes:` instead.

- The patch lacks a `Cc: stable@vger.kernel.org` tag, which would be appropriate if this is meant to fix a user-visible regression.

**Nit:** The commit message `[Why & How]` marker is an AMD-internal convention — no issue, just noting it.

**Verdict:** The change itself looks correct and safe. The main feedback items are:
1. Fix the `Fixes:` tag to reference a commit hash (or change to `Link:`/`Closes:`)
2. Confirm the FPU bounding box change (which affects all memory types) is intentional
3. Consider adding `Cc: stable@vger.kernel.org` if this should be backported

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Generated by Claude Code Patch Reviewer