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Wed, 20 May 2026 05:35:54 +0000 From: Biju Das To: Prabhakar , Laurent Pinchart , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , magnus.damm CC: "dri-devel@lists.freedesktop.org" , "linux-renesas-soc@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Fabrizio Castro , Prabhakar Mahadev Lad Subject: RE: [PATCH v4 4/5] drm: renesas: rz-du: Move mode_valid logic to per-SoC clock limits Thread-Topic: [PATCH v4 4/5] drm: renesas: rz-du: Move mode_valid logic to per-SoC clock limits Thread-Index: AQHc56nK9BJ9tFiG1kiCI4Ue74glYbYWZP+A Date: Wed, 20 May 2026 05:35:54 +0000 Message-ID: References: <20260519160825.4082566-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20260519160825.4082566-5-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20260519160825.4082566-5-prabhakar.mahadev-lad.rj@bp.renesas.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=bp.renesas.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: bp.renesas.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TY3PR01MB11346.jpnprd01.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 73686d1b-7c6f-4fcd-4c81-08deb631a93e X-MS-Exchange-CrossTenant-originalarrivaltime: 20 May 2026 05:35:54.1383 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 53d82571-da19-47e4-9cb4-625a166a4a2a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: TtGo1LUw6o8Sz/2jhI6S77EICPyrzxHiCijePRQ7kX0EzXLwe8Sq0RvZtSvxMZkbCkIgOz21fphyqHpzKDf8wey9tt8v3oZA0z7SMLXv4MU= X-MS-Exchange-Transport-CrossTenantHeadersStamped: OSZPR01MB8687 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi Prabhakar, Thanks for the patch. > -----Original Message----- > From: Prabhakar > Sent: 19 May 2026 17:08 > Subject: [PATCH v4 4/5] drm: renesas: rz-du: Move mode_valid logic to per= -SoC clock limits >=20 > From: Lad Prabhakar >=20 > Move pixel clock validation from a fixed encoder check to per SoC constra= ints stored in > rzg2l_du_device_info. >=20 > Pixel clock limits differ across SoCs in the RZ DU family and cannot be e= xpressed by a single shared > rule. For example, RZ/G2UL and RZ/G2L limit the DPAD0 pixel clock to a na= rrow window, while other SoCs > such as RZ/T2H require a wider operating range. >=20 > Add mode_clock_min and mode_clock_max fields to rzg2l_du_device_info to d= escribe the supported pixel > clock range for each SoC. Update > rzg2l_du_encoder_mode_valid() to check these bounds when evaluating > DPAD0 outputs, returning MODE_CLOCK_LOW when the pixel clock falls below = mode_clock_min and > MODE_CLOCK_HIGH when it exceeds mode_clock_max. >=20 > Populate the pixel clock limits for both the RZ/G2UL (R9A07G043U) and RZ/= G2L (R9A07G044) variants to a > minimum of 20875 kHz and a maximum of > 83500 kHz. >=20 > Signed-off-by: Lad Prabhakar > --- > v3->v4: > - Dropped per pad limits > - Updated commit message to reflect the change in approach. >=20 > v2->v3: > - Moved clock limits from device_info to output_routing to allow > per-output constraints. > - Updated commit message to reflect the change in approach. >=20 > v1->v2: > - Dropped storing info pointer in struct rzg2l_du_encoder as it's not nee= ded. > --- > drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c | 6 +++++- > drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h | 4 ++++ > drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c | 9 ++++++++- > 3 files changed, 17 insertions(+), 2 deletions(-) >=20 > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c b/drivers/gpu/d= rm/renesas/rz- > du/rzg2l_du_drv.c > index 0fef33a5a089..1e4b9f38c55b 100644 > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c > @@ -35,6 +35,8 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a07= g043u_info =3D { > .port =3D 0, > }, > }, > + .mode_clock_min =3D 20875, > + .mode_clock_max =3D 83500, > }; >=20 > static const struct rzg2l_du_device_info rzg2l_du_r9a07g044_info =3D { @= @ -48,7 +50,9 @@ static const > struct rzg2l_du_device_info rzg2l_du_r9a07g044_info =3D { > .possible_outputs =3D BIT(0), > .port =3D 1, > } > - } > + }, > + .mode_clock_min =3D 20875, > + .mode_clock_max =3D 83500, > }; >=20 > static const struct rzg2l_du_device_info rzg2l_du_r9a09g057_info =3D { d= iff --git > a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h b/drivers/gpu/drm/renesas/= rz-du/rzg2l_du_drv.h > index 58806c2a8f2b..885558eb9547 100644 > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h > @@ -44,10 +44,14 @@ struct rzg2l_du_output_routing { > * struct rzg2l_du_device_info - DU model-specific information > * @channels_mask: bit mask of available DU channels > * @routes: array of CRTC to output routes, indexed by output (RZG2L_DU_= OUTPUT_*) > + * @mode_clock_min: minimum pixel clock in kHz > + * @mode_clock_max: maximum pixel clock in kHz > */ > struct rzg2l_du_device_info { > unsigned int channels_mask; > struct rzg2l_du_output_routing routes[RZG2L_DU_OUTPUT_MAX]; > + u32 mode_clock_min; > + u32 mode_clock_max; > }; >=20 > #define RZG2L_DU_MAX_CRTCS 1 > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c b/drivers/g= pu/drm/renesas/rz- > du/rzg2l_du_encoder.c > index 0e567b57a408..56220139a149 100644 > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c > @@ -50,8 +50,15 @@ rzg2l_du_encoder_mode_valid(struct drm_encoder *encode= r, > const struct drm_display_mode *mode) { > struct rzg2l_du_encoder *renc =3D to_rzg2l_encoder(encoder); > + struct rzg2l_du_device *rcdu =3D to_rzg2l_du_device(renc->base.dev); > + const struct rzg2l_du_device_info *info =3D rcdu->info; >=20 > - if (renc->output =3D=3D RZG2L_DU_OUTPUT_DPAD0 && mode->clock > 83500) > + if (renc->output !=3D RZG2L_DU_OUTPUT_DPAD0) > + return MODE_OK; > + > + if (info->mode_clock_min && mode->clock < info->mode_clock_min) I will avoid checking the first part as it is mandatory for SoCs with DPI s= upport and DPI check above make sure that this part of the code is reachable only = for DPI output. > + return MODE_CLOCK_LOW; > + if (info->mode_clock_max && mode->clock > info->mode_clock_max) Same here.=20 Cheers, Biju > return MODE_CLOCK_HIGH; >=20 > return MODE_OK; > -- > 2.54.0