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Mon, 11 May 2026 13:58:43 -0700 (PDT) X-Received: by 2002:a05:6a00:428a:b0:83d:b11f:7979 with SMTP id d2e1a72fcca58-83eebbf4d69mr76903b3a.29.1778533122756; Mon, 11 May 2026 13:58:42 -0700 (PDT) Received: from [192.168.1.3] ([106.222.228.93]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8396563f049sm24664326b3a.7.2026.05.11.13.58.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 May 2026 13:58:42 -0700 (PDT) Message-ID: Date: Tue, 12 May 2026 02:28:34 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/5] drm/msm/a8xx: Fix RSCC offset To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rob Clark , Sean Paul , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org References: <20260512-glymur-gpu-dt-v3-0-84232dc21c03@oss.qualcomm.com> <20260512-glymur-gpu-dt-v3-1-84232dc21c03@oss.qualcomm.com> From: Akhil P Oommen Content-Language: en-US In-Reply-To: <20260512-glymur-gpu-dt-v3-1-84232dc21c03@oss.qualcomm.com> Content-Type: text/plain; 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Update the > virtual base address of rscc to point to the correct address. > > Signed-off-by: Akhil P Oommen Missed the Fixes tag: Fixes: 50e8a557d8d3 ("drm/msm/a8xx: Add support for A8x GMU") -Akhil > --- > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > index 1b44b9e21ad8..cab4c46c6cf2 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > @@ -2357,7 +2357,12 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) > goto err_mmio; > } > } else if (adreno_is_a8xx(adreno_gpu)) { > - gmu->rscc = gmu->mmio + 0x19000; > + /* > + * On a8xx , RSCC lives at GPU base + 0x50000, which falls > + * inside the GPU's kgsl_3d0_reg_memory range rather than the > + * GMU's. > + */ > + gmu->rscc = gpu->mmio + 0x50000; > } else { > gmu->rscc = gmu->mmio + 0x23000; > } >