From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Akhil P Oommen <akhilpo@oss.qualcomm.com>,
Rob Clark <robin.clark@oss.qualcomm.com>,
Sean Paul <sean@poorly.run>,
Konrad Dybcio <konradybcio@kernel.org>,
Dmitry Baryshkov <lumag@kernel.org>,
Abhinav Kumar <abhinav.kumar@linux.dev>,
Jessica Zhang <jesszhan0024@gmail.com>,
Marijn Suijten <marijn.suijten@somainline.org>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Antonino Maniscalco <antomani103@gmail.com>,
Connor Abbott <cwabbott0@gmail.com>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>
Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 01/16] drm/msm/a8xx: Fix the ticks used in submit traces
Date: Tue, 24 Mar 2026 10:48:14 +0100 [thread overview]
Message-ID: <b0ce15a6-b2b4-4059-93fd-9b4b0b4360c8@oss.qualcomm.com> (raw)
In-Reply-To: <20260324-a8xx-gpu-batch2-v1-1-fc95b8d9c017@oss.qualcomm.com>
On 3/23/26 9:12 PM, Akhil P Oommen wrote:
> GMU_ALWAYS_ON_COUNTER_* registers got moved in A8x, but currently, A6x
> register offsets are used in the submit traces instead of A8x offsets.
> To fix this, refactor a bit and use adreno_gpu->funcs->get_timestamp()
> everywhere.
>
> While we are at it, update a8xx_gmu_get_timestamp() to use the GMU AO
> counter.
>
> Fixes: 288a93200892 ("drm/msm/adreno: Introduce A8x GPU Support")
> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> ---
[...]
> -static int a6xx_gmu_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
> +static u64 a6xx_gmu_get_timestamp(struct msm_gpu *gpu)
> {
> struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
>
> - *value = read_gmu_ao_counter(a6xx_gpu);
> -
> - return 0;
> + return read_gmu_ao_counter(a6xx_gpu);
Can we instead make read_gmu_ao_counter() take a struct msm_gpu * and drop
this wrapper? Other callers also already have a ptr of that type
[...]
> -int a8xx_gmu_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
> +static u64 read_gmu_ao_counter(struct a6xx_gpu *a6xx_gpu)
Similarly here (also I know this is a static symbol, but keeping an
a8xx_ prefix would be nice
[...]
> case MSM_PARAM_TIMESTAMP:
> if (adreno_gpu->funcs->get_timestamp) {
> - int ret;
> -
> pm_runtime_get_sync(&gpu->pdev->dev);
> - ret = adreno_gpu->funcs->get_timestamp(gpu, value);
> + *value = (uint64_t) adreno_gpu->funcs->get_timestamp(gpu);
"u64", I think checkpathch will also warn about whitespace after a typecast
Konrad
next prev parent reply other threads:[~2026-03-24 9:48 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-23 20:12 [PATCH 00/16] drm/msm: A8xx Support - Batch 2 Akhil P Oommen
2026-03-23 20:12 ` [PATCH 01/16] drm/msm/a8xx: Fix the ticks used in submit traces Akhil P Oommen
2026-03-24 9:48 ` Konrad Dybcio [this message]
2026-03-24 21:32 ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 02/16] drm/msm/a6xx: Switch to preemption safe AO counter Akhil P Oommen
2026-03-24 9:51 ` Konrad Dybcio
2026-03-24 21:32 ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 03/16] drm/msm/a6xx: Correct OOB usage Akhil P Oommen
2026-03-24 21:32 ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 04/16] drm/msm/a6xx: Add support for Debug HFI Q Akhil P Oommen
2026-03-24 21:32 ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 05/16] drm/msm/adreno: Coredump on GPU/GMU init failures Akhil P Oommen
2026-03-24 9:53 ` Konrad Dybcio
2026-03-24 21:32 ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 06/16] drm/msm/a6xx: Use barriers while updating HFI Q headers Akhil P Oommen
2026-03-23 20:45 ` Rob Clark
2026-03-23 21:29 ` Dmitry Baryshkov
2026-03-23 21:35 ` Akhil P Oommen
2026-03-24 21:32 ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 07/16] drm/msm/a6xx: Use packed structs for HFI Akhil P Oommen
2026-03-24 21:32 ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 08/16] drm/msm/a6xx: Update HFI definitions Akhil P Oommen
2026-03-24 10:00 ` Konrad Dybcio
2026-03-24 21:32 ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 09/16] drm/msm/adreno: Implement gx_is_on() for A8x Akhil P Oommen
2026-03-24 10:03 ` Konrad Dybcio
2026-03-24 21:32 ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 10/16] drm/msm/a6xx: Fix gpu init from secure world Akhil P Oommen
2026-03-24 10:07 ` Konrad Dybcio
2026-03-24 21:32 ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 11/16] drm/msm/a8xx: Add SKU table for A840 Akhil P Oommen
2026-03-24 21:32 ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 12/16] drm/msm/a6xx: Add SKU detection support for X2-85 Akhil P Oommen
2026-03-23 20:37 ` Rob Clark
2026-03-23 21:34 ` Akhil P Oommen
2026-03-23 21:34 ` Dmitry Baryshkov
2026-03-24 10:09 ` Konrad Dybcio
2026-03-24 21:32 ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 13/16] drm/msm/a8xx: Implement IFPC support for A840 Akhil P Oommen
2026-03-24 10:13 ` Konrad Dybcio
2026-03-24 21:32 ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 14/16] drm/msm/a8xx: Preemption " Akhil P Oommen
2026-03-24 10:18 ` Konrad Dybcio
2026-03-24 21:32 ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 15/16] drm/msm/a6xx: Enable Preemption on X2-85 Akhil P Oommen
2026-03-24 21:32 ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 16/16] drm/msm/adreno: Expose a PARAM to check AQE support Akhil P Oommen
2026-03-23 21:36 ` Dmitry Baryshkov
2026-03-23 22:54 ` Connor Abbott
2026-03-24 10:19 ` Konrad Dybcio
2026-03-24 21:32 ` Claude review: " Claude Code Review Bot
2026-03-24 21:32 ` Claude review: drm/msm: A8xx Support - Batch 2 Claude Code Review Bot
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