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Wed, 8 Apr 2026 10:37:47 +0000 From: Tommaso Merciai To: tomm.merciai@gmail.com, geert@linux-m68k.org, laurent.pinchart@ideasonboard.com Cc: linux-renesas-soc@vger.kernel.org, biju.das.jz@bp.renesas.com, Tommaso Merciai , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Magnus Damm , Laurent Pinchart , Tomi Valkeinen , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v6 00/21] Add support for DU and DSI on the Renesas RZ/G3E SoC Date: Wed, 8 Apr 2026 12:36:45 +0200 Message-ID: X-Mailer: git-send-email 2.43.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: FR4P281CA0140.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:b8::8) To TYCPR01MB11947.jpnprd01.prod.outlook.com (2603:1096:400:3e1::6) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYCPR01MB11947:EE_|OS7PR01MB13668:EE_ X-MS-Office365-Filtering-Correlation-Id: f7321b02-aeb8-41ab-867c-08de955adfdc X-LD-Processed: 53d82571-da19-47e4-9cb4-625a166a4a2a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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RZ/G3E SoC has 2 LCD controller (LCDC0 and LCDC1), both are composed of Frame Compression Processor (FCPVD), Video Signal Processor (VSPD), and Display Unit (DU). LCDC0 is connected to LVDS (single or dual channel) and DSI. LCDC1 is connected to LVDS (single ch), DSI, and GPIO (Parallel I/F). Thanks & Regards, Tommaso v5->v6: - Rebased on top of next-20260406 - PATCH 1: Fixed rzv2h_cpg_plldsi_smux_clk_register() removed u8 width, mask variables and replaced with direct use of smux.width and clk_div_mask(smux.width). - PATCH 9: New patch. - PATCH 10: Extend patternProperties from "^port@[0-1]$" to "^port@[0-3]$" and explicitly disable port@2 and port@3 for existing SoCs that do not expose them. Reworked ports numbering + improved/fixed ports descriptions in the bindings documentation. Improved commit body. - PATCH 15: Aligned ports numbering with the bindings changes. - PATCH 20: Update ports numbering accordingly to the latest DT bindings. v4->v5: - Rebased on top of next-20260211 - PATCH 9: Dropped renesas,id property. - PATCH 10: Collected tag. - PATCH 14: Fixed RG2L_DU_FEATURE_SMUX2_DSI_CLK to RZG2L_DU_FEATURE_SMUX2_DSI_CLK Added features field documentation. - PATCH 19: Rename du0_out_dsi0 into du0_out_dsi. Rename du1_out_dsi0 into du1_out_dsi. Drop renesas,id entry from DU nodes. - PATCH 20: Use DU0 -> DSI instead of DU1 -> DSI. v3->v4: - Rebased on top of next-20260130 - PATCH 1: Fixed build error: https://lore.kernel.org/oe-kbuild-all/202601311423.gWtJuxiU-lkp@intel.com/ v2->v3: - PATCH 1: Added missing defines for duty num/den. v1->v2: - Rebased on top of next-20260129. - PATCH 1: Added rzv2h_cpg_plldsi_smux_{get,set}_duty_cycle clock operations to allow the DRM driver to query and configure the appropriate clock path based on the required output duty cycle. Updated commit message accordingly. - PATCH 2-5: Collected tags. - PATCH 6: Moved clk_ids to match enum order. - PATCH 7: Collected GUytterhoeven tag. Fixed "dsi_0_vclk2" position to match order. - PATCH 8: Collected GUytterhoeven tag. - PATCH 9: Use single compatible string instead of multiple compatible strings for the two DU instances, leveraging a 'renesas,id' property to differentiate between DU0 and DU1. Updated commit message. - PATCH 10: Removed oneOf from clocks property, which is not sufficient to differentiate between RZ/G3E, RZ/V2H(P) and RZ/G2L. Use the already existing vclk instead of vclk1 for RZ/G3E DSI bindings. Updated allOf. - PATCH 14: Instead of using clk-provider API to select the right parent clock, just set the correct duty cycle based on the output. Updated commit message accordingly. - PATCH 15-16: Collected tags. - PATCH 17: Squashed fcpvd0 and fcpvd1 patches into a single patch. Collected tags. - PATCH 18: Squashed vspd0 and vspd1 patches into a single patch. Collected tags. - PATCH 19: Reworked DU nodes to use single compatible. Use vclk instead of vclk1 for DSI Node and set to the right position. - PATCH 20: Fixed: dsi, du and adv7535 are part of the R9A09G047E57 SMARC SoM board then add entries in the rzg3e-smarc-som.dtsi instead of using the r9a09g047e57-smarc-du1-adv7535.dtsi. Tommaso Merciai (21): clk: renesas: rzv2h: Add PLLDSI clk mux support clk: renesas: r9a09g047: Add CLK_PLLETH_LPCLK support clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1} clocks clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1}_DIV7 clocks clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1}_CSDIV clocks clk: renesas: r9a09g047: Add support for SMUX2_DSI{0,1}_CLK clk: renesas: r9a09g047: Add support for DSI clocks and resets clk: renesas: r9a09g047: Add support for LCDC{0,1} clocks and resets dt-bindings: display: renesas,rzg2l-du: Refuse port@1 for RZ/G2UL dt-bindings: display: renesas,rzg2l-du: Add support for RZ/G3E SoC dt-bindings: display: bridge: renesas,dsi: Add support for RZ/G3E SoC drm: renesas: rz-du: mipi_dsi: Add out_port to OF data drm: renesas: rz-du: mipi_dsi: Add RZ_MIPI_DSI_FEATURE_GPO0R feature drm: renesas: rz-du: mipi_dsi: Add support for RZ/G3E drm: renesas: rz-du: Add RZ/G3E support media: dt-bindings: media: renesas,vsp1: Document RZ/G3E media: dt-bindings: media: renesas,fcp: Document RZ/G3E SoC arm64: dts: renesas: r9a09g047: Add fcpvd{0,1} nodes arm64: dts: renesas: r9a09g047: Add vspd{0,1} nodes arm64: dts: renesas: r9a09g047: Add DU{0,1} and DSI nodes arm64: dts: renesas: r9a09g047e57-smarc: Enable DU0 and DSI support .../bindings/display/bridge/renesas,dsi.yaml | 144 ++++++++++---- .../bindings/display/renesas,rzg2l-du.yaml | 31 ++- .../bindings/media/renesas,fcp.yaml | 2 + .../bindings/media/renesas,vsp1.yaml | 1 + arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 172 +++++++++++++++++ .../boot/dts/renesas/rzg3e-smarc-som.dtsi | 114 +++++++++++ drivers/clk/renesas/r9a09g047-cpg.c | 84 ++++++++ drivers/clk/renesas/rzv2h-cpg.c | 181 ++++++++++++++++++ drivers/clk/renesas/rzv2h-cpg.h | 12 ++ drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c | 48 +++++ drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c | 28 ++- drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h | 12 ++ .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 113 ++++++++++- .../drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h | 3 + include/linux/clk/renesas.h | 20 ++ 15 files changed, 919 insertions(+), 46 deletions(-) -- 2.43.0