From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Akhil P Oommen <akhilpo@oss.qualcomm.com>,
Rob Clark <robin.clark@oss.qualcomm.com>,
Sean Paul <sean@poorly.run>,
Konrad Dybcio <konradybcio@kernel.org>,
Dmitry Baryshkov <lumag@kernel.org>,
Abhinav Kumar <abhinav.kumar@linux.dev>,
Jessica Zhang <jesszhan0024@gmail.com>,
Marijn Suijten <marijn.suijten@somainline.org>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Antonino Maniscalco <antomani103@gmail.com>,
Connor Abbott <cwabbott0@gmail.com>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>
Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 02/16] drm/msm/a6xx: Switch to preemption safe AO counter
Date: Tue, 24 Mar 2026 10:51:17 +0100 [thread overview]
Message-ID: <deb68834-f384-46d8-81a3-9eff88deaef7@oss.qualcomm.com> (raw)
In-Reply-To: <20260324-a8xx-gpu-batch2-v1-2-fc95b8d9c017@oss.qualcomm.com>
On 3/23/26 9:12 PM, Akhil P Oommen wrote:
> CP_ALWAYS_ON_COUNTER is not save-restored during preemption, so it won't
> provide accurate data about the 'submit' when preemption is enabled.
> Switch to CP_ALWAYS_ON_CONTEXT which is preemption safe.
>
> Fixes: e7ae83da4a28 ("drm/msm/a6xx: Implement preemption for a7xx targets")
> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index 14d5b5e266f7..93bf2c40bfb9 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -345,7 +345,7 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
> * GPU registers so we need to add 0x1a800 to the register value on A630
> * to get the right value from PM4.
> */
> - get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER,
> + get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_CONTEXT,
> rbmemptr_stats(ring, index, alwayson_start));
>
> /* Invalidate CCU depth and color */
> @@ -386,7 +386,7 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
>
> get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0),
> rbmemptr_stats(ring, index, cpcycles_end));
> - get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER,
> + get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_CONTEXT,
> rbmemptr_stats(ring, index, alwayson_end));
>
> /* Write the fence to the scratch register */
> @@ -478,10 +478,10 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
>
> if (adreno_is_a8xx(adreno_gpu)) {
> rbbm_perfctr_cp0 = REG_A8XX_RBBM_PERFCTR_CP(0);
> - cp_always_on_counter = REG_A8XX_CP_ALWAYS_ON_COUNTER;
> + cp_always_on_counter = REG_A8XX_CP_ALWAYS_ON_CONTEXT;
I'm a little worried about mixing the names here - KGSL uses both of
these registers (A6XX_KERNEL_PROFILE vs A6XX_KERNEL_PROFILE_CONTEXT)
to track different fields of the struct adreno_drawobj_profile_entry
Konrad
next prev parent reply other threads:[~2026-03-24 9:51 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-23 20:12 [PATCH 00/16] drm/msm: A8xx Support - Batch 2 Akhil P Oommen
2026-03-23 20:12 ` [PATCH 01/16] drm/msm/a8xx: Fix the ticks used in submit traces Akhil P Oommen
2026-03-24 9:48 ` Konrad Dybcio
2026-03-24 21:32 ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 02/16] drm/msm/a6xx: Switch to preemption safe AO counter Akhil P Oommen
2026-03-24 9:51 ` Konrad Dybcio [this message]
2026-03-24 21:32 ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 03/16] drm/msm/a6xx: Correct OOB usage Akhil P Oommen
2026-03-24 21:32 ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 04/16] drm/msm/a6xx: Add support for Debug HFI Q Akhil P Oommen
2026-03-24 21:32 ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 05/16] drm/msm/adreno: Coredump on GPU/GMU init failures Akhil P Oommen
2026-03-24 9:53 ` Konrad Dybcio
2026-03-24 21:32 ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 06/16] drm/msm/a6xx: Use barriers while updating HFI Q headers Akhil P Oommen
2026-03-23 20:45 ` Rob Clark
2026-03-23 21:29 ` Dmitry Baryshkov
2026-03-23 21:35 ` Akhil P Oommen
2026-03-24 21:32 ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 07/16] drm/msm/a6xx: Use packed structs for HFI Akhil P Oommen
2026-03-24 21:32 ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 08/16] drm/msm/a6xx: Update HFI definitions Akhil P Oommen
2026-03-24 10:00 ` Konrad Dybcio
2026-03-24 21:32 ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 09/16] drm/msm/adreno: Implement gx_is_on() for A8x Akhil P Oommen
2026-03-24 10:03 ` Konrad Dybcio
2026-03-24 21:32 ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 10/16] drm/msm/a6xx: Fix gpu init from secure world Akhil P Oommen
2026-03-24 10:07 ` Konrad Dybcio
2026-03-24 21:32 ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 11/16] drm/msm/a8xx: Add SKU table for A840 Akhil P Oommen
2026-03-24 21:32 ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 12/16] drm/msm/a6xx: Add SKU detection support for X2-85 Akhil P Oommen
2026-03-23 20:37 ` Rob Clark
2026-03-23 21:34 ` Akhil P Oommen
2026-03-23 21:34 ` Dmitry Baryshkov
2026-03-24 10:09 ` Konrad Dybcio
2026-03-24 21:32 ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 13/16] drm/msm/a8xx: Implement IFPC support for A840 Akhil P Oommen
2026-03-24 10:13 ` Konrad Dybcio
2026-03-24 21:32 ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 14/16] drm/msm/a8xx: Preemption " Akhil P Oommen
2026-03-24 10:18 ` Konrad Dybcio
2026-03-24 21:32 ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 15/16] drm/msm/a6xx: Enable Preemption on X2-85 Akhil P Oommen
2026-03-24 21:32 ` Claude review: " Claude Code Review Bot
2026-03-23 20:12 ` [PATCH 16/16] drm/msm/adreno: Expose a PARAM to check AQE support Akhil P Oommen
2026-03-23 21:36 ` Dmitry Baryshkov
2026-03-23 22:54 ` Connor Abbott
2026-03-24 10:19 ` Konrad Dybcio
2026-03-24 21:32 ` Claude review: " Claude Code Review Bot
2026-03-24 21:32 ` Claude review: drm/msm: A8xx Support - Batch 2 Claude Code Review Bot
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