[PATCH v6 10/21] dt-bindings: display: renesas, rzg2l-du: Add support for RZ/G3E SoC

Tommaso Merciai
2026-04-08T10:39:12Z

The RZ/G3E SoC has 2 LCD controllers (LCDC), each containing a Frame
Compression Processor (FCPVD), a Video Signal Processor (VSPD), and a
Display Unit (DU).

- LCDC0 supports DSI and LVDS (single or dual-channel) outputs.
- LCDC1 supports DSI, LVDS (single-channel), and RGB outputs.

Add a new SoC-specific compatible string 'renesas,r9a09g047-du'.

Extend patternProperties from "^port@[0-1]$" to "^port@[0-3]$" to
allow up to four output ports, and explicitly disable port@2 and port@3
for existing SoCs that do not expose them.

Describe the four output ports of the RZ/G3E DU:

- port@0: DSI (available on both LCDC instances)
- port@1: DPAD / parallel RGB (LCDC1 only)
- port@2: LVDS channel 0 (LCDC0 only)
- port@3: LVDS channel 1 (available on both LCDC instances)

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
v5->v6:
- Extend patternProperties from "^port@[0-1]$" to "^port@[0-3]$" and
explicitly disable port@2 and port@3 for existing SoCs that do not expose
them.
- Reworked ports numbering + improved/fixed ports descriptions in the
bindings documentation.
- Improved commit body.

v4->v5:
- Dropped renesas,id property and updated bindings
accordingly.

v2->v3:
- No changes.

v2->v3:
- No changes.

v1->v2:
- Use single compatible string instead of multiple compatible strings
for the two DU instances, leveraging a 'renesas,id' property to
differentiate between DU0 and DU1.
- Updated commit message accordingly.

.../bindings/display/renesas,rzg2l-du.yaml | 30 ++++++++++++++++++-
1 file changed, 29 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
index 5add3b832eab..32da0b5ec88c 100644
--- a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
+++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
@@ -20,6 +20,7 @@ properties:
- enum:
- renesas,r9a07g043u-du # RZ/G2UL
- renesas,r9a07g044-du # RZ/G2{L,LC}
+ - renesas,r9a09g047-du # RZ/G3E
- renesas,r9a09g057-du # RZ/V2H(P)
- items:
- enum:
@@ -61,7 +62,7 @@ properties:
model-dependent. Each port shall have a single endpoint.

patternProperties:
- "^port@[0-1]$":
+ "^port@[0-3]$":
$ref: /schemas/graph.yaml#/properties/port
unevaluatedProperties: false

@@ -103,6 +104,8 @@ allOf:
port@0:
description: DPI
port@1: false
+ port@2: false
+ port@3: false

required:
- port@0
@@ -119,6 +122,8 @@ allOf:
description: DSI
port@1:
description: DPI
+ port@2: false
+ port@3: false

required:
- port@0
@@ -135,9 +140,32 @@ allOf:
port@0:
description: DSI
port@1: false
+ port@2: false
+ port@3: false

required:
- port@0
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a09g047-du
+ then:
+ properties:
+ ports:
+ properties:
+ port@0:
+ description: DSI
+ port@1:
+ description: DPAD
+ port@2:
+ description: LVDS, Channel 0
+ port@3:
+ description: LVDS, Channel 1
+
+ required:
+ - port@0
+ - port@3

examples:
# RZ/G2L DU
--
2.43.0