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[2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-38bf9ab6d4fsm3261211fa.34.2026.03.20.00.02.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2026 00:02:09 -0700 (PDT) Date: Fri, 20 Mar 2026 09:02:07 +0200 From: Dmitry Baryshkov To: Jonathan Marek Cc: Neil Armstrong , Alexander Koskovich , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Jeffrey Hugo , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org Subject: Re: [PATCH v3 4/4] drm/msm/dpu: fix video mode DSC INTF timing width calculation Message-ID: References: <20260319-dsi-rgb101010-support-v3-0-85b99df2d090@pm.me> <20260319-dsi-rgb101010-support-v3-4-85b99df2d090@pm.me> <1360a31d-669e-48df-a1be-f0af4a253cd7@linaro.org> <3gLK4s97giqqXagfHKhfiIHbfbl2snwfOj9dcTNGPUYi10w9-1EdATqzz1LPCVTpz4bLFYOm8u_Fl8PfC7t5yabows4UCzRKVwjraEWW6hc=@pm.me> <3f8763af-aad2-4d92-90c8-cfd290212503@linaro.org> <7fb9dd9d-13f9-7bba-93d1-08f42dd6ee38@marek.ca> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Proofpoint-ORIG-GUID: 57BJnw1QhgqLUd0YBq34Yi532BELmiAl X-Authority-Analysis: v=2.4 cv=EcjFgfmC c=1 sm=1 tr=0 ts=69bcf0f3 cx=c_pps a=5HAIKLe1ejAbszaTRHs9Ug==:117 a=xqWC_Br6kY4A:10 a=kj9zAlcOel0A:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=rjgCsHGJ4Y6OlbO_Df8A:9 a=CjuIK1q_8ugA:10 a=gYDTvv6II1OnSo0itH1n:22 X-Proofpoint-GUID: 57BJnw1QhgqLUd0YBq34Yi532BELmiAl X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzIwMDA1MSBTYWx0ZWRfX/1ngjP5RhQE0 Cg2b2J2qsL8Ly3XqOM5TrKUWNHKGkGUJ46mSErK/9Lx7Z/yZKPa8L/5EXoY6aK02Rin3OyWgQS3 ZVnw7sGSgFP+ZJgnoVoYABy+M7hxA+XHE3vRY+XbwuHuT5e46I2nvnwoagVBIQKxFNP93AiN4+j +GfpL+Tp09oZrpUjwYX/rV8V/Na4NVufwTx9QU6f+2ZAH477FLD0O60ZK9tiTAMNcdNpWC5zVPA kBRlMPS32MId0nLdyUc3UDl11piQeHd4OsPOQ03lPydrZ9kQC98PYsGttWWODowVibmiaGlAVff Jrivq7N/M0ElFB1hH+BvM0Q01xs08thKuASNo929V/hv4Tx4HrGVf3eJiqO4JWyvTvoZA15WgBB bcvFm0+ecKmWF+1WrUbqrT+QDlpNbV+4xL+peR9dctKkO6jxw9+61wnWM+J8QbJ9ZEU/pdbKGDZ k3DG6r+/Jx1bHUvxnRQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-19_04,2026-03-19_05,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 suspectscore=0 impostorscore=0 spamscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603200051 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Fri, Mar 20, 2026 at 12:25:00AM -0400, Jonathan Marek wrote: > On 3/19/26 9:45 PM, Dmitry Baryshkov wrote: > > On Thu, Mar 19, 2026 at 01:23:03PM -0400, Jonathan Marek wrote: > ... > > > > > > That's not how it works. INTF (which feeds DSI) is after DSC compression. > > > > > > INTF timings are always in RGB888 (24-bit) units. Ignoring widebus details, > > > the INTF timing should match what is programmed on the DSI side (hdisplay, > > > which is calculated as bytes per line / 3). > > > > > > (fwiw, the current "timing->width = ..." calculation here blames to me, but > > > what I wrote originally was just "timing->width = timing->width / 3" with a > > > comment about being incomplete.) > > > > > Okay. After reading the docs (sorry, it took a while). > > > > - When widebus is not enabled, the transfer is always 24 bit of > > compressed data. Thus if it is not in play, pclk and timing->width > > should be scaled by source_pixel_depth / compression_ratio / 24. In > > case of the code it is 'drm_dsc_get_bpp_int(dsc) / 24'. > > > > For RGB101010 / 8bpp DSC this should result in the PCLK being lowered > > by the factor of 3 (= 24 / (30 / 3.75)) > > > > - When widebus is in play (MDSS 6.x+, DSI 2.4+), the transfer takes > > more than 24 bits. In this case the PCLK and timing->width should be > > scaled exactly by the DSC compression ratio, which is > > 'drm_dsc_get_bpp_int(dsc) / (3 * dsc->bits_per_component). > > > > So, this piece of code needs to be adjusted to check for the widebus > > being enabled or not. > > > > The widebus adjustment on the MDP/INTF side is already in > dpu_hw_intf_setup_timing_engine: the "data width" is divided by 2 for 48-bit > widebus instead of 24-bit. there shouldn't be any other adjustment > (downstream doesn't have any other adjustment). > > a relevant downstream comment: "In DATABUS-WIDEN mode, MDP always sends out > 48-bit compressed data per pclk and on average, DSI consumes an amount of > compressed data equivalent to the uncompressed pixel depth per pclk." > > Based on that comment, this patch is correct, and the > ''drm_dsc_get_bpp_int(dsc) / (3 * dsc->bits_per_component)' adjustment only > applies to DSI. (note: newer downstream looks like it would divide by 3.75 > here, which doesn't make sense. older downstream would divide by 3 here. I > guess downstream is broken now and video mode + 10-bit dsc doesn't get > tested?) I guess, the downstream might be broken wrt. the widebus being enabled or not. > > on DSI side, "uncompressed pixel depth" shouldn't matter either: DSI only > sees the compressed data. But based on that comment, when widebus is > enabled, by setting DSI_VID_CFG0_DST_FORMAT(?) to 30bpp, then the DSI pclk > is in 30-bit units instead of 24-bits. And with this series DSI side ends up > with the right result if 30bpp format and widebus is enabled. -- With best wishes Dmitry