[PATCH v4 19/39] drm/msm/dp: Add support to enable MST in mainlink control

Yongxing Mou
2026-04-10T09:35:33Z

From: Abhinav Kumar <quic_abhinavk@quicinc.com>

Add support to program the MST enable bit in the mainlink control
register when an MST session is active or being disabled.

Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
---
drivers/gpu/drm/msm/dp/dp_ctrl.c | 17 +++++++++++++++++
drivers/gpu/drm/msm/dp/dp_reg.h | 4 ++++
2 files changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index 6f25145ef214..9513de81abc4 100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
@@ -255,6 +255,19 @@ int msm_dp_ctrl_mst_send_act(struct msm_dp_ctrl *msm_dp_ctrl)
return 0;
}

+static void msm_dp_ctrl_mst_config(struct msm_dp_ctrl_private *ctrl, bool enable)
+{
+ u32 mainlink_ctrl;
+
+ mainlink_ctrl = msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_CTRL);
+ if (enable)
+ mainlink_ctrl |= DP_MAINLINK_CTRL_MST_EN;
+ else
+ mainlink_ctrl &= ~DP_MAINLINK_CTRL_MST_EN;
+
+ msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, mainlink_ctrl);
+}
+
/*
* NOTE: resetting DP controller will also clear any pending HPD related interrupts
*/
@@ -2669,6 +2682,9 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel *

msm_dp_ctrl_lane_mapping(ctrl);
msm_dp_setup_peripheral_flush(ctrl);
+ if (ctrl->mst_active)
+ msm_dp_ctrl_mst_config(ctrl, true);
+
if (msm_dp_panel->stream_id == DP_STREAM_0)
msm_dp_ctrl_config_ctrl_link(ctrl);

@@ -2726,6 +2742,7 @@ void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl)
phy = ctrl->phy;

msm_dp_ctrl_mainlink_disable(ctrl);
+ msm_dp_ctrl_mst_config(ctrl, false);

msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl);

diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h
index 237325d52dbd..87eaaefa014d 100644
--- a/drivers/gpu/drm/msm/dp/dp_reg.h
+++ b/drivers/gpu/drm/msm/dp/dp_reg.h
@@ -128,6 +128,10 @@
#define DP_MAINLINK_FLUSH_MODE_UPDATE_SDP FIELD_PREP(DP_MAINLINK_CTRL_FLUSH_MODE_MASK, 1)
#define DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE FIELD_PREP(DP_MAINLINK_CTRL_FLUSH_MODE_MASK, 3)
#define DP_MAINLINK_FB_BOUNDARY_SEL (0x02000000)
+#define DP_MAINLINK_CTRL_ECF_MODE BIT(26)
+#define DP_MAINLINK_CTRL_MST_ACTIVE BIT(8)
+#define DP_MAINLINK_CTRL_MST_EN (DP_MAINLINK_CTRL_ECF_MODE | \
+ DP_MAINLINK_CTRL_MST_ACTIVE)

#define REG_DP_STATE_CTRL (0x00000004)
#define DP_STATE_CTRL_LINK_TRAINING_PATTERN1 (0x00000001)

--
2.43.0