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[2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5a3eeefbb1csm1497199e87.63.2026.04.11.10.55.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Apr 2026 10:55:54 -0700 (PDT) Date: Sat, 11 Apr 2026 20:55:52 +0300 From: Dmitry Baryshkov To: Yongxing Mou Cc: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Abhinav Kumar Subject: Re: [PATCH v4 13/39] drm/msm/dp: introduce stream_id for each DP panel Message-ID: References: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> <20260410-msm-dp-mst-v4-13-b20518dea8de@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260410-msm-dp-mst-v4-13-b20518dea8de@oss.qualcomm.com> X-Authority-Analysis: v=2.4 cv=PuijqQM3 c=1 sm=1 tr=0 ts=69da8b2f cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=xqWC_Br6kY4A:10 a=kj9zAlcOel0A:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=lDrsiWV98Tgi0JVLTm0A:9 a=CjuIK1q_8ugA:10 a=a_PwQJl-kcHnX1M80qC6:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: jUARU-s_TcjNDO1k9bdkoHdUDEph82dg X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDExMDE1OSBTYWx0ZWRfX6vbCd058Rzsd hv0kF7MCG/Zgm2KOdXjKUp8KOl4UNAlgSQhY/VO+4FyVn+Jy5Jo/s9iPXe//smjycQZD23L2Xo3 pMuq52mwdRVMWQIT0AaaOGESF1a64lnY80iAoY8HSV5C3wo0IynNDevVXljrrsH9t9CsewRpJ84 rc9tRHiMrQWhGoQlaCtsgF/JtD4bxXT0WLC8P7UZNcpRp3DFiUyAeoVemNhM9fWT5At75Xk5M1p 9+TKnr2d/tG0qhdLyL7lAjYMlYx+PZOn5uMHdYsfAZAXb/IC/+5s2Xm+qBDBgs2EabX02YSJBH1 31ofWNmdlOEP3B0LrK0upRpLX2qJ7IjhJGnXd4j6mErOUUEDD29CKh4cyx3b3vx/MsVZq/Kv6RG q+HB4wwu0vdYyb6s8MsuEJxWUBg3wpDW1QDrdnJ6PWQE1drVT7R8966b7jffV3Al19125sB7+eh BQ5bUgDKEH4UahZMUXw== X-Proofpoint-GUID: jUARU-s_TcjNDO1k9bdkoHdUDEph82dg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-11_05,2026-04-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 spamscore=0 phishscore=0 malwarescore=0 clxscore=1015 impostorscore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604110159 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Fri, Apr 10, 2026 at 05:33:48PM +0800, Yongxing Mou wrote: > From: Abhinav Kumar > > With MST, each DP controller can handle multiple streams. > There shall be one dp_panel for each stream but the dp_display > object shall be shared among them. To represent this abstraction, > create a stream_id for each DP panel which shall be set by the > MST stream. For SST, default this to stream 0. > > Use the stream ID to control the pixel clock of that respective > stream by extending the clock handles and state tracking of the > DP pixel clock to an array of max supported streams. The maximum > streams currently is 4. Please mention that panels are going to be dynamically assigned to actual stream IDs. > > Signed-off-by: Abhinav Kumar > Signed-off-by: Yongxing Mou > --- > drivers/gpu/drm/msm/dp/dp_ctrl.c | 57 +++++++++++++++++++++++-------------- > drivers/gpu/drm/msm/dp/dp_ctrl.h | 2 +- > drivers/gpu/drm/msm/dp/dp_display.c | 24 ++++++++++++++-- > drivers/gpu/drm/msm/dp/dp_display.h | 2 ++ > drivers/gpu/drm/msm/dp/dp_panel.h | 11 +++++++ > 5 files changed, 71 insertions(+), 25 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c > index 120ec00884e5..fb6396727628 100644 > --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c > +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c > @@ -127,7 +127,7 @@ struct msm_dp_ctrl_private { > unsigned int num_link_clks; > struct clk_bulk_data *link_clks; > > - struct clk *pixel_clk; > + struct clk *pixel_clk[DP_STREAM_MAX]; > > union phy_configure_opts phy_opts; > > @@ -139,7 +139,7 @@ struct msm_dp_ctrl_private { > > bool core_clks_on; > bool link_clks_on; > - bool stream_clks_on; > + bool stream_clks_on[DP_STREAM_MAX]; > }; > > static inline u32 msm_dp_read_ahb(const struct msm_dp_ctrl_private *ctrl, u32 offset) > @@ -2176,39 +2176,40 @@ static bool msm_dp_ctrl_send_phy_test_pattern(struct msm_dp_ctrl_private *ctrl) > return success; > } > > -static int msm_dp_ctrl_on_pixel_clk(struct msm_dp_ctrl_private *ctrl, unsigned long pixel_rate) > +static int msm_dp_ctrl_on_pixel_clk(struct msm_dp_ctrl_private *ctrl, unsigned long pixel_rate, > + enum msm_dp_stream_id stream_id) > { > int ret; > > - ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); > + ret = clk_set_rate(ctrl->pixel_clk[stream_id], pixel_rate * 1000); > if (ret) { > DRM_ERROR("Failed to set pixel clock rate. ret=%d\n", ret); > return ret; > } > > - if (ctrl->stream_clks_on) { > + if (ctrl->stream_clks_on[stream_id]) { > drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n"); > } else { > - ret = clk_prepare_enable(ctrl->pixel_clk); > + ret = clk_prepare_enable(ctrl->pixel_clk[stream_id]); > if (ret) { > DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret); > return ret; > } > - ctrl->stream_clks_on = true; > + ctrl->stream_clks_on[stream_id] = true; > } > > return ret; > } > > -void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl) > +void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl, enum msm_dp_stream_id stream_id) > { > struct msm_dp_ctrl_private *ctrl; > > ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); > > - if (ctrl->stream_clks_on) { > - clk_disable_unprepare(ctrl->pixel_clk); > - ctrl->stream_clks_on = false; > + if (ctrl->stream_clks_on[stream_id]) { > + clk_disable_unprepare(ctrl->pixel_clk[stream_id]); > + ctrl->stream_clks_on[stream_id] = false; > } > } > > @@ -2228,7 +2229,7 @@ static int msm_dp_ctrl_process_phy_test_request(struct msm_dp_ctrl_private *ctrl > * running. Add the global reset just before disabling the > * link clocks and core clocks. > */ > - msm_dp_ctrl_off_pixel_clk(&ctrl->msm_dp_ctrl); > + msm_dp_ctrl_off_pixel_clk(&ctrl->msm_dp_ctrl, ctrl->panel->stream_id); Why are we using ctrl->panel again here for the stream-related functions? Didn't you got rid of its usage few patches ago? > msm_dp_ctrl_off_link(&ctrl->msm_dp_ctrl); > > ret = msm_dp_ctrl_on_link(&ctrl->msm_dp_ctrl); > @@ -2238,7 +2239,7 @@ static int msm_dp_ctrl_process_phy_test_request(struct msm_dp_ctrl_private *ctrl > } > > pixel_rate = ctrl->panel->msm_dp_mode.drm_mode.clock; > - ret = msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate); > + ret = msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate, ctrl->panel->stream_id); And here... > > msm_dp_ctrl_send_phy_test_pattern(ctrl); > > @@ -1451,6 +1469,8 @@ void msm_dp_display_atomic_enable(struct msm_dp *msm_dp_display) > > dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); > > + msm_dp_display_set_stream_info(msm_dp_display, dp->panel, 0); DP_STREAM_0 > + > rc = msm_dp_display_enable(dp); > if (rc) > DRM_ERROR("DP display enable failed, rc=%d\n", rc); -- With best wishes Dmitry