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[2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-38bf9753c7dsm2623321fa.13.2026.03.19.18.45.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Mar 2026 18:45:34 -0700 (PDT) Date: Fri, 20 Mar 2026 03:45:31 +0200 From: Dmitry Baryshkov To: Jonathan Marek Cc: Neil Armstrong , Alexander Koskovich , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Jeffrey Hugo , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org Subject: Re: [PATCH v3 4/4] drm/msm/dpu: fix video mode DSC INTF timing width calculation Message-ID: References: <20260319-dsi-rgb101010-support-v3-0-85b99df2d090@pm.me> <20260319-dsi-rgb101010-support-v3-4-85b99df2d090@pm.me> <1360a31d-669e-48df-a1be-f0af4a253cd7@linaro.org> <3gLK4s97giqqXagfHKhfiIHbfbl2snwfOj9dcTNGPUYi10w9-1EdATqzz1LPCVTpz4bLFYOm8u_Fl8PfC7t5yabows4UCzRKVwjraEWW6hc=@pm.me> <3f8763af-aad2-4d92-90c8-cfd290212503@linaro.org> <7fb9dd9d-13f9-7bba-93d1-08f42dd6ee38@marek.ca> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Disposition: inline Content-Transfer-Encoding: quoted-printable In-Reply-To: <7fb9dd9d-13f9-7bba-93d1-08f42dd6ee38@marek.ca> X-Proofpoint-GUID: XDcyFlMWAI4GNRf4jSaSV4aaI7GEFgFx X-Proofpoint-ORIG-GUID: XDcyFlMWAI4GNRf4jSaSV4aaI7GEFgFx X-Authority-Analysis: v=2.4 cv=ApTjHe9P c=1 sm=1 tr=0 ts=69bca6c2 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=xqWC_Br6kY4A:10 a=8nJEP1OIZ-IA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=KKAkSRfTAAAA:8 a=SUsfgI6VF5ffP_QSSRUA:9 a=3ZKOabzyN94A:10 a=wPNLvfGTeEIA:10 a=dawVfQjAaf238kedN5IG:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzIwMDAxMiBTYWx0ZWRfX07sX6UTZppp3 vYx01iJ4CpovSdCpXGPbt6XVR8feQ2aiiBg7l84ZZ3f/s2goWWsrdPCQ8Sz7hDDOu6hAIcMtC6d ASCVFx6Rcm/wgm5TOXKf1d8D+8oVW7oxb1ye/hbujZ5APU8CBHvBAVKVJBZ4OtO1DYfO5yD+hRD MDEuCP3PfMbQqbwJyp0+SCQUH73JgXVIYZQmzNkI/PV+r43HkwaNZbAmdFnfOhs17jllWBQ3S+V MK9bOhXxGfTqb1Q/PuzJ8kRZqmSrqZCX1D+pT2U1Wy8ddQQ9TnZVLgFcl7ViVAwcubzlBTTCIGd gwv1ngFLtL27LDV7O1q0ZeFGPYUNiUI4ZX8GgwD7abF1+YnAY2CTiJ3vx3Gmqxd2EQSWu+hnUrH hggcdoNyYZSHjBMlBj88d12fPyGM+hEHeRrMK3io9LIEYA85PGzjavwoSTjrH085U+kfX3A+72v AMEERfGngzQT4ZTZ8jQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-19_04,2026-03-19_05,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 suspectscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 spamscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603200012 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Thu, Mar 19, 2026 at 01:23:03PM -0400, Jonathan Marek wrote: > On 3/19/26 10:54 AM, Neil Armstrong wrote: > > On 3/19/26 15:40, Alexander Koskovich wrote: > > > On Thursday, March 19th, 2026 at 10:13 AM, Neil Armstrong > > > wrote: > > >=20 > > > > Hi, > > > >=20 > > > > On 3/19/26 12:58, Alexander Koskovich wrote: > > > > > Using bits_per_component * 3 as the divisor for the compressed IN= TF > > > > > timing width produces constant FIFO errors for the BOE BF068MWM-T= D0 > > > > > panel due to bits_per_component being 10 which results in a divis= or > > > > > of 30 instead of 24. > > > > >=20 > > > > > Regardless of the compression ratio and pixel depth, 24 bits of > > > > > compressed data are transferred per pclk, so the divisor should > > > > > always be 24. > > > >=20 > > > > Not true with widebus, specify why 24 and because DSI widebus is > > > > not implemented yet. > > > >=20 >=20 > DSI widebus is implemented, and always used when available. The adjustment > for DSI widebus just doesn't happen in this function. >=20 > > > > >=20 > > > > > Signed-off-by: Alexander Koskovich > > > > > --- > > > > > =A0=A0 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 9 += +++----- > > > > > =A0=A0 1 file changed, 4 insertions(+), 5 deletions(-) > > > > >=20 > > > > > diff --git > > > > > a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > > > > > b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > > > > > index 0ba777bda253..5419ef0be137 100644 > > > > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > > > > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > > > > > @@ -122,19 +122,18 @@ static void drm_mode_to_intf_timing_params( > > > > > =A0=A0=A0=A0=A0=A0 } > > > > >=20 > > > > > =A0=A0=A0=A0=A0=A0 /* > > > > > -=A0=A0=A0=A0 * for DSI, if compression is enabled, then divide t= he > > > > > horizonal active > > > > > -=A0=A0=A0=A0 * timing parameters by compression ratio. bits of 3 > > > > > components(R/G/B) > > > > > -=A0=A0=A0=A0 * is compressed into bits of 1 pixel. > > > > > +=A0=A0=A0=A0 * For DSI, if DSC is enabled, 24 bits of compressed= data are > > > > > +=A0=A0=A0=A0 * transferred per pclk regardless of the source pix= el depth. > > > > > =A0=A0=A0=A0=A0=A0=A0 */ > > > > > =A0=A0=A0=A0=A0=A0 if (phys_enc->hw_intf->cap->type !=3D INTF_DP = && > > > > > timing->compression_en) { > > > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 struct drm_dsc_config *dsc =3D > > > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 dpu_encoder_g= et_dsc_config(phys_enc->parent); > > > > > + > > > > Drop this change > > > >=20 > > > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 /* > > > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 * TODO: replace drm_dsc_get_bpp= _int with logic to handle > > > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 * fractional part if there is f= raction > > > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 */ > > > > > -=A0=A0=A0=A0=A0=A0=A0 timing->width =3D timing->width * drm_dsc_= get_bpp_int(dsc) / > > > > > -=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 (dsc->bits_per_com= ponent * 3); > > > > > +=A0=A0=A0=A0=A0=A0=A0 timing->width =3D timing->width * drm_dsc_= get_bpp_int(dsc) / 24; > > > >=20 > > > > It would be helpful to somehow show that 24 is 8 * 3, 8 being > > > > the byte width and 3 the compression ratio. > > >=20 > > > Can you clarify what the 3 represents? My panel should have a 3.75:1 > > > compression > > > ratio (30/8) so the final divisor of 24 would be wrong for my panel > > > if its the > > > compression ratio? > >=20 > > So my guess is that while the exact ratio on the DSI lanes is 3.75:1, > > the ratio > > used to calculate the INTF timings is 3, then the DSC encoder probably > > does the > > magic to feed 10bpp into a 3.75:1 ratio over the DSI lanes. > >=20 >=20 > That's not how it works. INTF (which feeds DSI) is after DSC compression. >=20 > INTF timings are always in RGB888 (24-bit) units. Ignoring widebus detail= s, > the INTF timing should match what is programmed on the DSI side (hdisplay, > which is calculated as bytes per line / 3). >=20 > (fwiw, the current "timing->width =3D ..." calculation here blames to me,= but > what I wrote originally was just "timing->width =3D timing->width / 3" wi= th a > comment about being incomplete.) >=20 Okay. After reading the docs (sorry, it took a while). - When widebus is not enabled, the transfer is always 24 bit of compressed data. Thus if it is not in play, pclk and timing->width should be scaled by source_pixel_depth / compression_ratio / 24. In case of the code it is 'drm_dsc_get_bpp_int(dsc) / 24'. For RGB101010 / 8bpp DSC this should result in the PCLK being lowered by the factor of 3 (=3D 24 / (30 / 3.75)) - When widebus is in play (MDSS 6.x+, DSI 2.4+), the transfer takes more than 24 bits. In this case the PCLK and timing->width should be scaled exactly by the DSC compression ratio, which is 'drm_dsc_get_bpp_int(dsc) / (3 * dsc->bits_per_component). So, this piece of code needs to be adjusted to check for the widebus being enabled or not. > > In dsi_adjust_pclk_for_compression, the pclk is adjusted to take in > > account bits_per_component, > > so I presume the actual DSI pclk _is_=A0 timing->width * > > drm_dsc_get_bpp_int(dsc) / (dsc->bits_per_component * 3), > > which is your 3.75:1, but the INTF needs to generate timing->width * > > drm_dsc_get_bpp_int(dsc) / (8 * 3) pixels > > to the DSC encoder which will emit timing->width * > > drm_dsc_get_bpp_int(dsc) / (dsc->bits_per_component * 3) pixels. > >=20 >=20 > The hdisplay calculation in dsi_adjust_pclk_for_compression (which only > affects the clock rate) seems to be wrong, and I think Alexander's panel > must be running at a 20% lower clock because of it. dsi_timing_setup has = the > right hdisplay adjustment. That function also needs to be adjusted accordingly. I think only the dsi_timing_setup() is correct at this point. Note, widebus / not-widebus cases should be handled separately. > > In any case, 24 _is_ 3 * 8, 3 being the DSC compression ratio on the > > INTF side. In this case DSC compression ratio is 3.75, so it's not true. --=20 With best wishes Dmitry