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[2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5a3eeee11f6sm1524462e87.44.2026.04.11.10.34.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Apr 2026 10:34:49 -0700 (PDT) Date: Sat, 11 Apr 2026 20:34:46 +0300 From: Dmitry Baryshkov To: Yongxing Mou Cc: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 05/39] drm/msm/dp: splite msm_dp_ctrl_config_ctrl() into link parts and stream parts Message-ID: References: <20260410-msm-dp-mst-v4-0-b20518dea8de@oss.qualcomm.com> <20260410-msm-dp-mst-v4-5-b20518dea8de@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260410-msm-dp-mst-v4-5-b20518dea8de@oss.qualcomm.com> X-Authority-Analysis: v=2.4 cv=PuijqQM3 c=1 sm=1 tr=0 ts=69da863b cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=xqWC_Br6kY4A:10 a=kj9zAlcOel0A:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=lIPaWChcOsILjI9_6t8A:9 a=CjuIK1q_8ugA:10 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-ORIG-GUID: sLlidzFrrXPgXOPaUxhoMkppEcOYMQhx X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDExMDE1NCBTYWx0ZWRfX5XSYS9UlGxzj Y4djlUtVMP6YQlwHMxTFPNzBt2U5kXhheCphW1l0TxBfV362BEcoqZXQKFyFBpGCrYpGx+FzSIL qcXs22fatHaEGXWq1HnqhizMavxPQ5xtxy1VS59Q7RYLJKU8xC2bUKBAymgy9rymSHZse/NAfbZ lPNl/uD2I2Poyso0Pu9wUd9Okn4mkINWLzsS6uqReRph2aXMr5HFt0t/molIueOw9PauPtqHq1c 1TA4FZiwQKZz4HI4hI4742K4Wu0roWUV7itwPZXqeEZY+Ko1Ft9kQTcgso9XCoqC2YBR5r770nw ET/nf7kgxYpRPWv95bMwcJlIZX8P1QiecXcMFQ5zhTqe8yZwzMv6ANHM5/9bvKuRl3mXJZS9pHV zSwXIqy4xTe5pRmxMy8xqk7vKyADAdwncvt3cZaBW1yceO5wGxUZyniFGQoSkdsyeitQDpKdvQh 1YKf9nPyBnzZEg+N3sg== X-Proofpoint-GUID: sLlidzFrrXPgXOPaUxhoMkppEcOYMQhx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-11_04,2026-04-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 spamscore=0 phishscore=0 malwarescore=0 clxscore=1015 impostorscore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604110154 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Fri, Apr 10, 2026 at 05:33:40PM +0800, Yongxing Mou wrote: > The DP_CONFIGURATION_CTRL register contains both link-level and > stream-specific fields. Currently, msm_dp_ctrl_config_ctrl() configures > all of them together. Separates the configuration into link parts and > streams part for support MST. > > Signed-off-by: Yongxing Mou > --- > drivers/gpu/drm/msm/dp/dp_ctrl.c | 43 ++++++++++++++++++++++++++-------------- > 1 file changed, 28 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c > index 476346e3ac19..85315467b5d0 100644 > --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c > +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c > @@ -388,26 +388,41 @@ void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl) > drm_dbg_dp(ctrl->drm_dev, "mainlink off\n"); > } > > -static void msm_dp_ctrl_config_ctrl(struct msm_dp_ctrl_private *ctrl) > +static void msm_dp_ctrl_config_ctrl_streams(struct msm_dp_ctrl_private *ctrl, > + struct msm_dp_panel *msm_dp_panel) > { > u32 config = 0, tbd; > + > + config = msm_dp_read_link(ctrl, REG_DP_CONFIGURATION_CTRL); > + > + if (msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420) > + config |= DP_CONFIGURATION_CTRL_RGB_YUV; /* YUV420 */ > + > + tbd = msm_dp_link_get_test_bits_depth(ctrl->link, > + msm_dp_panel->msm_dp_mode.bpp); > + > + config |= tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT; > + > + if (msm_dp_panel->psr_cap.version) > + config |= DP_CONFIGURATION_CTRL_SEND_VSC; > + > + drm_dbg_dp(ctrl->drm_dev, "stream DP_CONFIGURATION_CTRL=0x%x\n", config); > + > + msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL, config); You have an RMW cycle here. Please document what prevents it from racing with the concurrent msm_dp_ctrl_config_ctrl_link(). > +} > + > +static void msm_dp_ctrl_config_ctrl_link(struct msm_dp_ctrl_private *ctrl) > +{ > + u32 config = 0; > const u8 *dpcd = ctrl->panel->dpcd; > > /* Default-> LSCLK DIV: 1/4 LCLK */ > config |= (2 << DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT); > > - if (ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420) > - config |= DP_CONFIGURATION_CTRL_RGB_YUV; /* YUV420 */ > - > /* Scrambler reset enable */ > if (drm_dp_alternate_scrambler_reset_cap(dpcd)) > config |= DP_CONFIGURATION_CTRL_ASSR; > > - tbd = msm_dp_link_get_test_bits_depth(ctrl->link, > - ctrl->panel->msm_dp_mode.bpp); > - > - config |= tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT; > - > /* Num of Lanes */ > config |= ((ctrl->link->link_params.num_lanes - 1) > << DP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT); > @@ -421,10 +436,7 @@ static void msm_dp_ctrl_config_ctrl(struct msm_dp_ctrl_private *ctrl) > config |= DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN; > config |= DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK; > > - if (ctrl->panel->psr_cap.version) > - config |= DP_CONFIGURATION_CTRL_SEND_VSC; > - > - drm_dbg_dp(ctrl->drm_dev, "DP_CONFIGURATION_CTRL=0x%x\n", config); > + drm_dbg_dp(ctrl->drm_dev, "link DP_CONFIGURATION_CTRL=0x%x\n", config); > > msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL, config); > } > @@ -450,7 +462,8 @@ static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private *ctrl > msm_dp_ctrl_lane_mapping(ctrl); > msm_dp_setup_peripheral_flush(ctrl); > > - msm_dp_ctrl_config_ctrl(ctrl); > + msm_dp_ctrl_config_ctrl_link(ctrl); > + msm_dp_ctrl_config_ctrl_streams(ctrl, ctrl->panel); > > test_bits_depth = msm_dp_link_get_test_bits_depth(ctrl->link, ctrl->panel->msm_dp_mode.bpp); > colorimetry_cfg = msm_dp_link_get_colorimetry_config(ctrl->link); > @@ -1628,7 +1641,7 @@ static int msm_dp_ctrl_link_train(struct msm_dp_ctrl_private *ctrl, > u8 assr; > struct msm_dp_link_info link_info = {0}; > > - msm_dp_ctrl_config_ctrl(ctrl); > + msm_dp_ctrl_config_ctrl_link(ctrl); > > link_info.num_lanes = ctrl->link->link_params.num_lanes; > link_info.rate = ctrl->link->link_params.rate; > > -- > 2.43.0 > -- With best wishes Dmitry