From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/msm/dsi: fix hdisplay calculation when programming dsi registers Date: Sun, 15 Feb 2026 19:06:21 +1000 Message-ID: In-Reply-To: <20260214105145.105308-1-mitltlatltl@gmail.com> References: <20260214105145.105308-1-mitltlatltl@gmail.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Overall Series Review Subject: drm/msm/dsi: fix hdisplay calculation when programming dsi registers Author: Pengyu Luo Patches: 1 Reviewed: 2026-02-15T19:06:21.715308 --- This is a single patch fixing the `hdisplay` calculation in `dsi_timing_setup= ()` for DSC-compressed video when widebus is enabled. The commit message clai= ms the current code only works for a 3:1 compressed ratio and that a panel wi= th DSC BPP=3D8 and BPC=3D10 would get wrong values because the default `bits_= per_pclk` of 24 doesn't account for pixel formats with different bit depths. The patch renames `bytes_per_pclk` to `bits_per_pclk`, replaces the hardcoded= 3/6 values with `mipi_dsi_pixel_format_to_bpp()` (when widebus is enabled) o= r 24 (when not), and adjusts the division to work in bits rather than bytes. = It also removes the `MIPI_DSI_MODE_VIDEO` guard, so widebus now takes effect = for video mode too (previously it was CMD-only). The core mathematical concern is whether `mipi_dsi_pixel_format_to_bpp(msm_ho= st->format)` is the correct divisor. The commit message says this should cros= s-compare with `dsi_adjust_pclk_for_compression()`, which uses `dsc->bits_per= _component * 3` as its uncompressed-bpp divisor. For 8bpc panels with RGB888 = these agree (both yield 24), but they diverge for 10bpc or 12bpc panels where= `bpc * 3` would be 30 or 36 while `mipi_dsi_pixel_format_to_bpp(MIPI_DSI_FMT= _RGB888)` still returns 24. This discrepancy warrants clarification. --- Generated by Claude Code Patch Reviewer