From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: Introduce DRM_RAS using generic netlink for RAS Date: Tue, 24 Feb 2026 10:45:41 +1000 Message-ID: In-Reply-To: <20260223060541.526397-7-riana.tauro@intel.com> References: <20260223060541.526397-7-riana.tauro@intel.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Overall Series Review Subject: Introduce DRM_RAS using generic netlink for RAS Author: Riana Tauro Patches: 6 Reviewed: 2026-02-24T10:45:41.469510 --- This series introduces a DRM RAS (Reliability, Availability, Serviceability) infrastructure over generic netlink, allowing GPU drivers to expose error counters to userspace in a standardized way. Patch 1 creates the core DRM RAS framework with netlink operations (list-nodes, get-error-counter). Patches 2-3 add the Xe driver's integration layer, and patches 4-5 implement PVC-specific GT and SoC error handling that feeds into the RAS counters. The overall architecture is reasonable: a global xarray of RAS nodes, a genl family with dump/do operations, and per-driver callbacks for querying error counters. The YAML-driven netlink spec and auto-generated headers follow modern kernel netlink conventions. The split between correctable and uncorrectable error nodes is a sensible design. However, there are several concrete bugs in the series. The netlink dumpit handlers have uninitialized return values when their loops don't execute. The `doit_reply_value` function leaks an skb on one error path. The Xe registration cleanup has both a `kfree(ERR_PTR(...))` crash and a partial-registration leak that could lead to use-after-free if a later node registration fails. The correctable SoC error path in patch 5 clears status registers without reading or counting the errors, which seems inconsistent with the goal of error counting. --- Generated by Claude Code Patch Reviewer