Claude review: drm/msm/a6xx: Fix the bogus protect error on X2-85

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Overall Series Review

Subject: drm/msm/a6xx: Fix the bogus protect error on X2-85
Author: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patches: 2
Reviewed: 2026-02-27T13:55:25.487020

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This is a single-patch fix for an incorrect `count_max` value in the X2-85 (Adreno) GPU protect register configuration, introduced in commit `01ff3bf27215`. The fix is correct and addresses a real hardware-visible bug where usermode drivers (UMD) were blocked from accessing the MMIO region.

The core issue is that `count_max` has **different semantics** between the a6xx and a8xx code paths. In `a6xx_set_cp_protect()`, `count_max` is the total number of protect registers, and the last entry is written to index `count_max - 1`. In `a8xx_set_cp_protect()`, `count_max` is used directly as the pipe protect register index for the "last span infinite range" entry. The x285 GPU was incorrectly given `count_max=64`, causing the infinite-range entry to be written to pipe register index 64, which is out of range (the hardware has pipe protect registers up to index 15). This meant the catch-all protection rule was never properly installed in the pipe-specific registers.

The fix is straightforward and correct, though I have minor suggestions below.

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