Claude review: Enable mdss1 Display Port for Qualcomm lemans-ride platform

[Claude Code Review Bot <claude-review@example.com>]

Overall Series Review

Subject: Enable mdss1 Display Port for Qualcomm lemans-ride platform
Author: Mani Chandana Ballary Kuntumalla <quic_mkuntuma@quicinc.com>
Patches: 5
Reviewed: 2026-02-27T12:26:29.297745

---

This 2-patch series adds device tree nodes for the second Mobile Display Subsystem (mdss1) on the Qualcomm SA8775P (Lemans) SoC, including DPTX0/DPTX1 controllers and eDP PHYs, and then enables them on the lemans-ride board.

The series is well-structured and closely follows the existing mdss0 patterns. The OPP table refactoring (moving them to root level for sharing between mdss0 and mdss1) is clean and was requested by the reviewer. The node structure, clock assignments, interrupt numbering, and port wiring all look correct and consistent with mdss0.

The series depends on an unmerged series (https://lore.kernel.org/all/20260128114853.2543416-1-quic_riteshk@quicinc.com/) which likely introduces `MASTER_MDP_CORE1_0`/`MASTER_MDP_CORE1_1` interconnect masters and `GCC_DISP1_HF_AXI_CLK`, and may also add the "ref" clock to the mdss0 PHYs. This dependency should be clearly noted for merge ordering.

**One notable concern**: The mdss1 eDP PHY nodes include a third clock (`GCC_EDP_REF_CLKREF_EN` / "ref") that the current upstream mdss0 eDP PHY nodes do not have. If the dependency series doesn't also add this clock to the mdss0 PHY nodes, this creates an inconsistency. Otherwise, the series looks ready to go.

---

---
Generated by Claude Code Patch Reviewer