From: Claude Code Review Bot <claude-review@example.com>
To: dri-devel-reviews@example.com
Subject: Claude review: (no cover subject)
Date: Tue, 03 Mar 2026 13:40:01 +1000 [thread overview]
Message-ID: <review-overall-20260302-glymur-fix-dp-bindings-reg-clocks-v2-0-e99b6f871e3b@oss.qualcomm.com> (raw)
In-Reply-To: <20260302-glymur-fix-dp-bindings-reg-clocks-v2-0-e99b6f871e3b@oss.qualcomm.com>
Overall Series Review
Subject: (no cover subject)
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>
Patches: 2
Reviewed: 2026-03-03T13:40:01.758671
---
This is a 2-patch series fixing Qualcomm Glymur DP controller device tree bindings. The changes are logically sound: Glymur's DP controllers have 4 ports in their register space (unlike similar platforms that only have 2), requiring 9 `reg` entries instead of 5. The series correctly separates Glymur into its own conditional block and updates the example node to match. Both patches are tagged for stable (v6.19), which is appropriate for binding fixes.
**One notable issue**: The patch perpetuates a pre-existing typo (`clocks-names` instead of `clock-names`) present in all existing conditional blocks in `dp-controller.yaml`. Since the property is defined as `clock-names` (line 101), all the `clocks-names` constraints in the `allOf` conditionals are effectively dead — they constrain a non-existent property and thus never enforce anything. This is worth flagging even though it's not introduced by this series.
The v2 was sent without a cover subject and the author noted it should be ignored; v3 is the corrected submission with identical patches.
---
Generated by Claude Code Patch Reviewer
prev parent reply other threads:[~2026-03-03 3:40 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-02 9:33 [PATCH v2 0/2] (no cover subject) Abel Vesa
2026-03-02 9:36 ` Abel Vesa
2026-03-03 3:40 ` Claude Code Review Bot [this message]
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