From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: (no cover subject) Date: Tue, 03 Mar 2026 13:40:01 +1000 Message-ID: In-Reply-To: <20260302-glymur-fix-dp-bindings-reg-clocks-v2-0-e99b6f871e3b@oss.qualcomm.com> References: <20260302-glymur-fix-dp-bindings-reg-clocks-v2-0-e99b6f871e3b@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Overall Series Review Subject: (no cover subject) Author: Abel Vesa Patches: 2 Reviewed: 2026-03-03T13:40:01.758671 --- This is a 2-patch series fixing Qualcomm Glymur DP controller device tree b= indings. The changes are logically sound: Glymur's DP controllers have 4 po= rts in their register space (unlike similar platforms that only have 2), re= quiring 9 `reg` entries instead of 5. The series correctly separates Glymur= into its own conditional block and updates the example node to match. Both= patches are tagged for stable (v6.19), which is appropriate for binding fi= xes. **One notable issue**: The patch perpetuates a pre-existing typo (`clocks-n= ames` instead of `clock-names`) present in all existing conditional blocks = in `dp-controller.yaml`. Since the property is defined as `clock-names` (li= ne 101), all the `clocks-names` constraints in the `allOf` conditionals are= effectively dead =E2=80=94 they constrain a non-existent property and thus= never enforce anything. This is worth flagging even though it's not introd= uced by this series. The v2 was sent without a cover subject and the author noted it should be i= gnored; v3 is the corrected submission with identical patches. --- Generated by Claude Code Patch Reviewer