From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: dt-bindings: display: msm: Fix reg ranges and clocks on Glymur Date: Wed, 04 Mar 2026 07:43:55 +1000 Message-ID: In-Reply-To: <20260303-glymur-fix-dp-bindings-reg-clocks-v4-1-1ebd9c7c2cee@oss.qualcomm.com> References: <20260303-glymur-fix-dp-bindings-reg-clocks-v4-1-1ebd9c7c2cee@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Overall Series Review Subject: dt-bindings: display: msm: Fix reg ranges and clocks on Glymur Author: Abel Vesa Patches: 2 Reviewed: 2026-03-04T07:43:55.780213 --- This is a single-patch fix for the Glymur DisplayPort DT bindings. It addre= sses two issues introduced in v6.19: the DP controller binding had incorrec= t register range constraints (5 instead of 9) by grouping Glymur with platf= orms that have a different register layout, and the MDSS example used wrong= /incomplete register addresses. The fix is straightforward and correct =E2= =80=94 it moves `qcom,glymur-dp` out of the `sc8280xp-dp`/`x1e80100-dp` gro= up into its own clause requiring all 9 register blocks, and updates the exa= mple to match. There is one minor issue to flag: the patch perpetuates a pre-existing typo= (`clocks-names` vs. `clock-names`). **Verdict**: Looks good overall. One minor issue worth fixing. --- --- Generated by Claude Code Patch Reviewer