From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: Two-pass MMU interval notifiers Date: Wed, 04 Mar 2026 07:09:16 +1000 Message-ID: In-Reply-To: <20260303133409.11609-1-thomas.hellstrom@linux.intel.com> References: <20260303133409.11609-1-thomas.hellstrom@linux.intel.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Overall Series Review Subject: Two-pass MMU interval notifiers Author: =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= Patches: 7 Reviewed: 2026-03-04T07:09:16.400260 --- This is a well-structured v3 series from Thomas Hellstrom that adds two-pass MMU interval notifier support to the mm core and then uses it in the Xe driver to pipeline TLB invalidations across multi-GPU setups. The motivation is clear: in multi-GPU scenarios, the current single-pass model serializes GPU TLB flush submit+wait per notifier, which doesn't scale. The two-pass approach allows submitting flushes to all GPUs first, then waiting for them all in a second pass. The design is sound overall: patch 1 provides the mm core infrastructure, patch 2 converts xe userptr to the two-pass model with a single embedded finish struct and fallback to synchronous operation, patch 3 refactors TLB invalidation into submit/wait halves, and patch 4 extends the deferred path to also pipeline the TLB flush itself. I found one clear bug (static local variable in `xe_vma_userptr_force_invalidate`) and have several concerns about the increasing complexity of the state machine in patches 2+4 and the growing per-userptr struct size. The mm core patch (1) looks correct. --- --- Generated by Claude Code Patch Reviewer