From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: Introduce DRM_RAS using generic netlink for RAS Date: Thu, 05 Mar 2026 13:47:40 +1000 Message-ID: In-Reply-To: <20260304074412.464435-7-riana.tauro@intel.com> References: <20260304074412.464435-7-riana.tauro@intel.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Overall Series Review Subject: Introduce DRM_RAS using generic netlink for RAS Author: Riana Tauro Patches: 6 Reviewed: 2026-03-05T13:47:40.227283 --- This series introduces a DRM RAS (Reliability, Availability, Serviceability= ) infrastructure over generic netlink, along with the first Xe driver imple= mentation for PVC (Ponte Vecchio). The architecture is reasonable: a core D= RM RAS layer manages nodes in an xarray, exposes them via genetlink, and dr= ivers register nodes with error counter callbacks. The series is at v10 and= has several acks/reviews, but there are still several bugs and design conc= erns worth addressing. **Key issues:** 1. **Memory leak in `doit_reply_value()`** =E2=80=94 `msg` skb is leaked on= `get_node_error_counter()` failure. 2. **Uninitialized `ret` in `drm_ras_nl_list_nodes_dumpit()`** =E2=80=94 re= turns garbage if xarray is empty. 3. **No locking around xarray access** =E2=80=94 concurrent register/unregi= ster vs. netlink queries is racy. 4. **`error-value` uses u32** =E2=80=94 but counters use `atomic_t` which c= an overflow; also `hweight32` accumulation can produce inflated counts. 5. **Correctable errors skip all register reads in SoC handler** =E2=80=94 = just clears with all-1s, losing diagnostic information. --- Generated by Claude Code Patch Reviewer