From: Claude Code Review Bot <claude-review@example.com>
To: dri-devel-reviews@example.com
Subject: Claude review: Re: [PATCH] drm/amd/display: fix resuming from S3 sleep for Renoir iGPU
Date: Mon, 09 Mar 2026 08:01:01 +1000 [thread overview]
Message-ID: <review-overall-202603080959.llKqWvRQ-lkp@intel.com> (raw)
In-Reply-To: <202603080959.llKqWvRQ-lkp@intel.com>
Overall Series Review
Subject: Re: [PATCH] drm/amd/display: fix resuming from S3 sleep for Renoir iGPU
Author: kernel test robot <lkp@intel.com>
Patches: 3
Reviewed: 2026-03-09T08:01:01.464269
---
This is a single-patch fix for a real regression on Renoir (DCN 2.1) iGPUs where resume from S3 sleep fails (black screen). The root cause analysis is correct: commit `4c595e75110e` migrated `MICROSECOND_TIME_BASE_DIV` register access from hwseq to the dccg component, but the dccg register table for DCN21 never included the `MICROSECOND_TIME_BASE_DIV` register offset. This means `REG_READ(MICROSECOND_TIME_BASE_DIV)` in `dccg2_is_s0i3_golden_init_wa_done()` reads from offset 0 (uninitialized), always returning the wrong value, causing the S0i3 golden init workaround to incorrectly trigger on every resume.
The fix is functional and addresses a real user-visible bug. However, there are several issues worth raising.
---
Generated by Claude Code Patch Reviewer
next prev parent reply other threads:[~2026-03-08 22:01 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-27 23:01 [bug report] 7.0-rc1 flip_done timed out: amd igpu off when resuming in laptop (regression) Rafael Passos
2026-03-04 12:27 ` Rafael Passos
2026-03-04 16:32 ` Alex Deucher
2026-03-08 0:04 ` [PATCH] drm/amd/display: fix resuming from S3 sleep for Renoir iGPU Rafael Passos
2026-03-08 8:19 ` kernel test robot
2026-03-08 22:01 ` Claude Code Review Bot [this message]
2026-03-08 16:23 ` kernel test robot
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