From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: Re: [PATCH] drm/amd/display: fix resuming from S3 sleep for Renoir iGPU Date: Mon, 09 Mar 2026 08:01:01 +1000 Message-ID: In-Reply-To: <202603080959.llKqWvRQ-lkp@intel.com> References: <202603080959.llKqWvRQ-lkp@intel.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Overall Series Review Subject: Re: [PATCH] drm/amd/display: fix resuming from S3 sleep for Renoir iGPU Author: kernel test robot Patches: 3 Reviewed: 2026-03-09T08:01:01.464269 --- This is a single-patch fix for a real regression on Renoir (DCN 2.1) iGPUs where resume from S3 sleep fails (black screen). The root cause analysis is correct: commit `4c595e75110e` migrated `MICROSECOND_TIME_BASE_DIV` register access from hwseq to the dccg component, but the dccg register table for DCN21 never included the `MICROSECOND_TIME_BASE_DIV` register offset. This means `REG_READ(MICROSECOND_TIME_BASE_DIV)` in `dccg2_is_s0i3_golden_init_wa_done()` reads from offset 0 (uninitialized), always returning the wrong value, causing the S0i3 golden init workaround to incorrectly trigger on every resume. The fix is functional and addresses a real user-visible bug. However, there are several issues worth raising. --- Generated by Claude Code Patch Reviewer