From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/msm/dpu: fix mismatch between power and frequency Date: Tue, 10 Mar 2026 12:42:46 +1000 Message-ID: In-Reply-To: <20260309063720.13572-1-yuanjie.yang@oss.qualcomm.com> References: <20260309063720.13572-1-yuanjie.yang@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Overall Series Review Subject: drm/msm/dpu: fix mismatch between power and frequency Author: yuanjie yang Patches: 1 Reviewed: 2026-03-10T12:42:46.926861 --- This is a single-patch fix for a real power/clock mismatch bug in the DPU (= Display Processing Unit) driver on Qualcomm SoCs. The problem is well-descr= ibed: during runtime suspend, `dev_pm_opp_set_rate(dev, 0)` drops the MMCX = power rail voltage to MIN_SVS, but the clock rate is not correspondingly lo= wered. On resume, `clk_bulk_prepare_enable()` re-enables the clock at its p= revious (high) rate while the rail is still at the low voltage, causing pot= ential instability. The fix is simple =E2=80=94 remove the `dev_pm_opp_set_rate(dev, 0)` call f= rom `dpu_runtime_suspend()`. This is a reasonable approach because: 1. The resume path (`dpu_runtime_resume`) never calls `dev_pm_opp_set_rate(= )` to restore the performance state, so there was already an asymmetry. 2. The performance state vote will be naturally cleaned up when clocks are = disabled via `clk_bulk_disable_unprepare()`, since the OPP framework and ru= ntime PM handle genpd voltage scaling when the device is fully suspended. 3. The active OPP rate is managed through `dpu_core_perf_crtc_update()` =E2= =86=92 `_dpu_core_perf_set_core_clk_rate()` during normal operation. --- Generated by Claude Code Patch Reviewer