From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: Fix Adaptive Sync SDP for PR with Link ON + Auxless ALPM Date: Thu, 12 Mar 2026 06:55:27 +1000 Message-ID: In-Reply-To: <20260311113611.3393194-1-ankit.k.nautiyal@intel.com> References: <20260311113611.3393194-1-ankit.k.nautiyal@intel.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Overall Series Review Subject: Fix Adaptive Sync SDP for PR with Link ON + Auxless ALPM Author: Ankit Nautiyal Patches: 20 Reviewed: 2026-03-12T06:55:27.715509 --- This 19-patch series from Ankit Nautiyal enables Adaptive Sync SDP for Panel Replay with Link ON and Auxless ALPM (Link-Off) on Intel display hardware. The first several patches clean up drm/dp header macros, fix existing bugs, and add preparatory infrastructure. Later patches add the actual PR+VRR AS SDP support, split AS SDP computation into early and late phases, and always enable AS SDP when source+sink support it. The series is generally well-structured and incrementally builds the feature. Some patches have Ville's R-b, indicating they've had prior review. However, there is one **critical bug** in patch 14 involving an incorrect burst DPCD write, and several other issues worth addressing. **Key issues:** 1. **Bug (Patch 14):** Burst write sends PANEL_REPLAY_CONFIG3 to wrong DPCD address (0x1b2 instead of 0x11a) 2. **Bug (Patch 18):** `intel_dp_get_as_sdp_revision()` returns `bool` but should return `int`/`u8` 3. **Patch ordering:** Patches 3 and 4 arrive out of order in the mbox (numbered 03/04 but message IDs -4 and -5 swapped) --- --- Generated by Claude Code Patch Reviewer