From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: Panel Replay BW optimization Date: Fri, 13 Mar 2026 14:30:26 +1000 Message-ID: In-Reply-To: <20260312050035.3493690-1-animesh.manna@intel.com> References: <20260312050035.3493690-1-animesh.manna@intel.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Overall Series Review Subject: Panel Replay BW optimization Author: Animesh Manna Patches: 13 Reviewed: 2026-03-13T14:30:26.626654 --- This is a v7 3-patch series adding Panel Replay bandwidth optimization support for DP 2.0 tunneling in the i915 display driver. The concept is straightforward: when a Panel Replay-enabled DP panel is idle with the link on, unused bandwidth can be reclaimed by external display agents (e.g., USB4 data). The series adds infrastructure to query the tunnel bridge's capability, programs the hardware register bit to enable it, and disables Panel Replay entirely when tunneling is active but the bridge doesn't support the optimization (per DP spec requirement). The series is generally clean and well-structured for a v7. A few issues noted below, ranging from a doc typo to a potential concern about deactivation path completeness. --- Generated by Claude Code Patch Reviewer