Claude review: drm/msm/dpu: calculate data_width like downstream

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Overall Series Review

Subject: drm/msm/dpu: calculate data_width like downstream
Author: Alexander Koskovich <akoskovich@pm.me>
Patches: 3
Reviewed: 2026-03-25T08:12:58.528087

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This is a single-patch fix to how the DPU INTF timing engine calculates the `data_width` (the data validity window) when DSC compression is enabled on DSI interfaces. The current upstream code derives `data_width` from `p->width`, which was already adjusted by a simplified compression ratio formula (`width * bpp_int / (bpc * 3)`). The patch replaces this with a calculation based on `msm_dsc_get_bytes_per_line()` (i.e., `slice_count * slice_chunk_size`), matching downstream/vendor behavior. It uses `DIV_ROUND_UP` to avoid truncation errors.

The approach is reasonable: using the actual DSC slice geometry (`slice_count * slice_chunk_size`) is more accurate than the existing approximation, which uses `drm_dsc_get_bpp_int()` and loses the fractional BPP. The pattern also mirrors how `dsi_host.c` already computes `hdisplay` for DSC.

**Overall: The patch looks correct in concept but has one notable concern.**

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