From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/msm/dpu: calculate data_width like downstream Date: Wed, 25 Mar 2026 08:12:58 +1000 Message-ID: In-Reply-To: <20260322-fix-data-width-calc-v2-1-d5f28136bc4e@pm.me> References: <20260322-fix-data-width-calc-v2-1-d5f28136bc4e@pm.me> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Overall Series Review Subject: drm/msm/dpu: calculate data_width like downstream Author: Alexander Koskovich Patches: 3 Reviewed: 2026-03-25T08:12:58.528087 --- This is a single-patch fix to how the DPU INTF timing engine calculates the `data_width` (the data validity window) when DSC compression is enabled on DSI interfaces. The current upstream code derives `data_width` from `p->width`, which was already adjusted by a simplified compression ratio formula (`width * bpp_int / (bpc * 3)`). The patch replaces this with a calculation based on `msm_dsc_get_bytes_per_line()` (i.e., `slice_count * slice_chunk_size`), matching downstream/vendor behavior. It uses `DIV_ROUND_UP` to avoid truncation errors. The approach is reasonable: using the actual DSC slice geometry (`slice_count * slice_chunk_size`) is more accurate than the existing approximation, which uses `drm_dsc_get_bpp_int()` and loses the fractional BPP. The pattern also mirrors how `dsi_host.c` already computes `hdisplay` for DSC. **Overall: The patch looks correct in concept but has one notable concern.** --- Generated by Claude Code Patch Reviewer