From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/msm/disp/dpu: consider SSPP line width during mode valid Date: Tue, 31 Mar 2026 17:55:49 +1000 Message-ID: In-Reply-To: <20260328-msm-next-v1-1-12ac4e27c670@oss.qualcomm.com> References: <20260328-msm-next-v1-1-12ac4e27c670@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Overall Series Review Subject: drm/msm/disp/dpu: consider SSPP line width during mode valid Author: Vishnu Saini Patches: 6 Reviewed: 2026-03-31T17:55:49.647743 --- This is a single patch that adds SSPP (Source Surface Pixel Processor) line= width as an additional constraint during mode validation in the DPU CRTC. = The intent is correct =E2=80=94 several Qualcomm targets (sm6150, sm6125, s= m6115, qcm2290, sm6375) have `max_linewidth` smaller than `max_mixer_width`= (e.g., sm6150: max_linewidth=3D2160, max_mixer_width=3D2560), meaning mode= s could pass `dpu_crtc_mode_valid()` but fail later in `atomic_check`. The code change itself is clean and straightforward. However, there is a ga= p in the fix. --- Generated by Claude Code Patch Reviewer