From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/amdgpu: replace PASID IDR with XArray Date: Wed, 01 Apr 2026 07:48:28 +1000 Message-ID: In-Reply-To: <20260331111808.16578-1-mikhail.v.gavrilov@gmail.com> References: <20260331111808.16578-1-mikhail.v.gavrilov@gmail.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Overall Series Review Subject: drm/amdgpu: replace PASID IDR with XArray Author: Mikhail Gavrilov Patches: 3 Reviewed: 2026-04-01T07:48:28.604416 --- This is a single-patch v6 series replacing an IDR+spinlock PASID allocator = with XArray to fix two locking bugs introduced by commit 8f1de51f49be. The = commit message is excellent =E2=80=94 it clearly describes both bugs, inclu= des the hardirq call chain, and documents the real-world trigger scenario. **However, the patch has a critical correctness bug: it does not actually f= ix the hardirq deadlock (bug #2) that it claims to fix.** The patch uses `x= a_erase()` and `xa_alloc_cyclic()`, which both use plain `xa_lock()`/`xa_un= lock()` (i.e., `spin_lock()`/`spin_unlock()`). The `XA_FLAGS_LOCK_IRQ` flag= does **not** make these wrapper functions use IRQ-safe locking =E2=80=94 i= t only affects the internal lock drop/reacquire path used during memory all= ocation inside the XArray internals. The v5 approach (explicit `xa_lock_irqsave`/`__xa_erase`) was actually on t= he right track. The v6 commit message states *"all xa operations use IRQ-sa= fe locking internally"* but this is incorrect. --- Generated by Claude Code Patch Reviewer