From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/i915/color: Enable SDR plane color pipeline Date: Sun, 12 Apr 2026 13:07:22 +1000 Message-ID: In-Reply-To: <20260408051514.608781-1-chaitanya.kumar.borah@intel.com> References: <20260408051514.608781-1-chaitanya.kumar.borah@intel.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Overall Series Review Subject: drm/i915/color: Enable SDR plane color pipeline Author: Chaitanya Kumar Borah Patches: 14 Reviewed: 2026-04-12T13:07:22.561946 --- This 13-patch series adds SDR plane color pipeline support to i915, building on the existing HDR plane color pipeline infrastructure and the DRM colorop framework. It introduces a new `DRM_COLOROP_FIXED_MATRIX` colorop type for fixed-function CSC blocks, adds pre/post-CSC LUT programming for SDR planes, and wires up YUV range correction through the colorop framework. The series is generally well-structured with a clean patch decomposition (DRM core type, i915 pipeline wiring, HW programming, refactoring, new features). However, there is a **critical bug** in how the new colorop-based CSC/range-correction interacts with the existing legacy YUV color handling in `glk_plane_color_ctl()`, which will cause register corruption for YUV framebuffers on SDR planes and a regression for limited-range YUV content even without using color pipelines. **Key issues:** 1. **Critical**: Conflicting CSC mode and YUV range correction programming paths in `glk_plane_color_ctl()` (Patches 3/12) 2. **Medium**: Hardcoded `plane - 3` offset for SDR plane register addressing (Patches 7/9) 3. **Minor**: Kernel-doc tag mismatch for `DRM_COLOROP_FM_YCBCR2020_FULL_RGB_NC` (Patch 1) 4. **Minor**: Post-CSC refactoring silently removes segment 0 programming (Patch 8) --- --- Generated by Claude Code Patch Reviewer