From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: accel/ivpu: Add support for limiting NPU frequency Date: Sun, 12 Apr 2026 12:19:40 +1000 Message-ID: In-Reply-To: <20260408150152.2093638-1-andrzej.kacprowski@linux.intel.com> References: <20260408150152.2093638-1-andrzej.kacprowski@linux.intel.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Overall Series Review Subject: accel/ivpu: Add support for limiting NPU frequency Author: Andrzej Kacprowski Patches: 1 Reviewed: 2026-04-12T12:19:40.349981 --- This is a single-patch series (v3) adding configurable NPU frequency limits= to the Intel IVPU accelerator driver. The feature introduces a new `freq/`= sysfs subdirectory with hardware info and configurable min/max frequency a= ttributes, a new JSM firmware message (`VPU_JSM_MSG_FREQ_CONFIG`), and lega= cy compatibility aliases for the existing top-level sysfs frequency attribu= tes. The overall design is reasonable: a `freq/` group for organized frequency a= ttributes, firmware communication via JSM messages, and conditional exposur= e of writable attributes only on 50XX+ devices. The code is generally clean= and follows existing driver patterns. However, there are several issues ra= nging from a type mismatch bug to missing access controls and cleanup conce= rns. **Key issues:** 1. **Type mismatch between function signature and internal callers** (`u16`= in declaration vs `u8` at call sites and `u32` in payload struct) 2. **No permission check on writable sysfs attributes** =E2=80=94 any user = can change NPU frequency 3. **Missing concurrency protection** for `cfg_min_ratio`/`cfg_max_ratio` 4. **Misleading comment** in `set_max_freq_store` 5. **`dpu_mhz_to_pll_ratio_lnl` used unconditionally** for MTL devices too 6. **Sysfs cleanup not handled** for manually-added files --- --- Generated by Claude Code Patch Reviewer