From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/rockchip: vop2: Add clock rate mode check Date: Sun, 12 Apr 2026 10:38:57 +1000 Message-ID: In-Reply-To: <20260409-vop2-clk-rate-check-v2-1-b207cfc427d7@collabora.com> References: <20260409-vop2-clk-rate-check-v2-1-b207cfc427d7@collabora.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Overall Series Review Subject: drm/rockchip: vop2: Add clock rate mode check Author: Sebastian Reichel Patches: 1 Reviewed: 2026-04-12T10:38:57.670124 --- This is a single RFC patch that adds pixel clock rate validation to the Roc= kchip VOP2 display driver's `mode_valid` callback. The approach is straight= forward and correct in principle: store a per-video-port maximum pixel cloc= k rate and reject modes that exceed it. The implementation is clean and min= imal. The main area of concern =E2=80=94 which the author explicitly flags via th= e RFC tag =E2=80=94 is the correctness of the `* 4` multiplier applied to t= he 600 MHz base clock for certain video ports. The rk3588 `* 4` multiplier = is well-supported by the existing code comment at `rockchip_vop2_reg.c:1572= ` ("4 pixclk/cycle on rk3588") and the `dclk_core_rate =3D v_pixclk >> 2` l= ogic. The rk3576 case is less clear. **Verdict**: The code change itself is correct and well-structured. The num= erical values need confirmation from the hardware vendor (Andy Yan), partic= ularly for rk3576. A couple of minor issues noted below. --- Generated by Claude Code Patch Reviewer