From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/nouveau: stability fixes for NVAC (MCP79/MCP7A) Date: Sun, 12 Apr 2026 10:25:00 +1000 Message-ID: In-Reply-To: <20260409172126.115441-1-marek@czernohous.de> References: <20260409172126.115441-1-marek@czernohous.de> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Overall Series Review Subject: drm/nouveau: stability fixes for NVAC (MCP79/MCP7A) Author: Marek Czernohous Patches: 4 Reviewed: 2026-04-12T10:25:00.599272 --- This is a 3-patch series targeting stability on NVAC (MCP79) hardware, cove= ring MSI re-arm, a NULL pointer guard in display teardown, and a DP link ch= eck retry. The author has clearly done real testing on hardware and the pro= blems described are plausible. However, there are significant issues with a= ccuracy in the commit messages and with the scope of the changes vs. what i= s described. **Patch 1** is the strongest patch =E2=80=94 it aligns g94 with its sibling= chipsets (g84, g92) that already use the PCI config space method =E2=80=94= but the commit message contains a factually incorrect claim about NVAA. **= Patch 2** adds a defensive NULL check that prevents a crash, but the "race = condition" explanation is questionable and the early-return path skips subs= tantial cleanup. **Patch 3** is the most concerning =E2=80=94 it adds a bla= nket 100ms sleep in a shared hot-plug work handler affecting all chipsets, = not just the claimed NV50/G94. The series would benefit from more accurate commit messages and, in at leas= t one case, a narrower or better-justified fix. --- --- Generated by Claude Code Patch Reviewer