From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: dt-bindings: display: ti, am65x-dss: Fix AM62L DSS reg and clock constraints Date: Sun, 12 Apr 2026 09:43:11 +1000 Message-ID: In-Reply-To: <20260410105955.843868-1-s-jain1@ti.com> References: <20260410105955.843868-1-s-jain1@ti.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Overall Series Review Subject: dt-bindings: display: ti, am65x-dss: Fix AM62L DSS reg and clock constraints Author: Swamil Jain Patches: 2 Reviewed: 2026-04-12T09:43:11.719203 --- This is a single patch (v3) fixing the DT binding for the AM62L DSS in `ti,am65x-dss.yaml`. The AM62L DSS has a single video port with only a "lite plane" (no VID plane, no OVR2, no VP2), but the original AM62L binding addition incorrectly reused the same 8-register, 3-clock constraints as the dual-video-port AM65x/AM625/AM62A7 variants. The fix is well-structured and uses two complementary mechanisms: 1. `oneOf` at the property level for `reg`/`reg-names` to define both valid register layouts (8-item for dual-VP and 5-item for AM62L). 2. `if`/`then`/`else` conditionals in `allOf` to bind the correct register/clock counts to the correct `compatible` string. The approach is clean and follows established dt-binding conventions. The `Fixes:` and `Cc: stable` tags are appropriate since the original AM62L binding would have validated incorrectly (requiring 8 registers and 3 clocks that don't exist on AM62L hardware). **Verdict: Patch looks correct and ready to apply, with minor observations noted below.** --- Generated by Claude Code Patch Reviewer