From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/rcar-du: Add support for DSI pipelines with DSC Date: Sat, 16 May 2026 09:29:57 +1000 Message-ID: In-Reply-To: <20260515-rcar-du-dsc-v3-0-164157820498@ideasonboard.com> References: <20260515-rcar-du-dsc-v3-0-164157820498@ideasonboard.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Overall Series Review Subject: drm/rcar-du: Add support for DSI pipelines with DSC Author: Tomi Valkeinen Patches: 8 Reviewed: 2026-05-16T09:29:57.304158 --- This is a well-structured 7-patch series adding DSC (Display Stream Compres= sion) bypass-mode support for Renesas R-Car V4H SoCs. The DSC IP block sits= between the DU and DSI1, and even when DSC encoding is not used, the block= must be powered for DSI1 output to function. The series correctly adds: cl= ock definition, DT binding, bridge driver, DSI pipeline adaptation, SoC DT = node, and board-level enablement for Sparrow Hawk and White Hawk. The overall design is sound =E2=80=94 a simple drm_bridge pass-through driv= er that powers the DSC block on/off via runtime PM. The pipeline re-wiring = in the DT and the `rcar_mipi_dsi_resolve_bridge()` helper in the DSI driver= are appropriate solutions for the architecture. There are a few issues to address, primarily around resource lifetime in th= e DSC driver (bridge reference leak, manual PM runtime management), and the= `mode_valid` clock check semantics. **Verdict**: Mostly ready. The bridge reference leak should be fixed before= merge; the other items are minor. --- --- Generated by Claude Code Patch Reviewer