From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: accel: ethosu: Add performance counter support Date: Sat, 16 May 2026 10:08:39 +1000 Message-ID: In-Reply-To: <20260515032625.1880618-1-robh@kernel.org> References: <20260515032625.1880618-1-robh@kernel.org> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Overall Series Review Subject: accel: ethosu: Add performance counter support Author: "Rob Herring (Arm)" Patches: 1 Reviewed: 2026-05-16T10:08:39.258984 --- This is a single-patch series (v2) adding PMU performance counter support to the Arm Ethos-U NPU accelerator driver. The implementation is modeled after V3D's perfmon subsystem. The design is straightforward: userspace creates a perfmon object with desired event counters, attaches it to job submissions (or sets it as a global monitor), and reads back accumulated counter values. The code uses XArray for ID allocation, refcounting for perfmon lifetime, and a per-device spinlock for protecting active perfmon state. Overall the patch is in reasonable shape for a v2 but has several issues that should be addressed before merging, ranging from a likely crash bug in `pmu_regs` initialization, to UAPI struct padding/alignment concerns, to locking and data-race issues. --- Generated by Claude Code Patch Reviewer