From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: gpu/drm: bridge: tc358768: Add delay after PLL setup Date: Mon, 25 May 2026 22:05:01 +1000 Message-ID: In-Reply-To: <20260520092628.47539-1-clamor95@gmail.com> References: <20260520092628.47539-1-clamor95@gmail.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Overall Series Review Subject: gpu/drm: bridge: tc358768: Add delay after PLL setup Author: Svyatoslav Ryhel Patches: 2 Reviewed: 2026-05-25T22:05:01.975192 --- This is a single-patch series adding a 20ms `msleep()` delay after PLL setu= p in the TC358768 DSI bridge driver. The fix addresses a real hardware issu= e on the TF700T (ASUS Transformer Pad Infinity) where the PLL reports lock = but the clock hasn't fully stabilized, resulting in a blank screen. The change is small, low-risk, and placed at the correct location. The exis= ting `tc358768_setup_pll()` already has a 1-2ms `usleep_range()` for PLL lo= ck, then enables `PLL_CKEN`. The new delay gives the clock output time to s= ettle after `PLL_CKEN` is asserted =E2=80=94 a distinct and valid concern f= rom the lock wait itself. The patch has a Tested-by tag on the affected har= dware. **Verdict**: Looks reasonable. One minor concern worth raising. --- Generated by Claude Code Patch Reviewer