From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/msm: Add PERFCNTR_CONFIG ioctl Date: Mon, 25 May 2026 21:26:27 +1000 Message-ID: In-Reply-To: <20260520162454.18391-1-robin.clark@oss.qualcomm.com> References: <20260520162454.18391-1-robin.clark@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Overall Series Review Subject: drm/msm: Add PERFCNTR_CONFIG ioctl Author: Rob Clark Patches: 17 Reviewed: 2026-05-25T21:26:27.022279 --- This is a well-structured v8 series from Rob Clark adding a `PERFCNTR_CONFI= G` ioctl to the MSM DRM driver for Adreno GPU performance counter collectio= n. The series is decomposed cleanly: remove old perf infrastructure, sync r= egister tables from Mesa, build up the perfcntr data structures, add the io= ctl and stream fd, then wire up IFPC support. All patches carry Reviewed-by= tags from Dmitry Baryshkov, Anna Maniscalco, and/or Akhil P Oommen. The overall design is sound =E2=80=94 global counters via an hrtimer-sample= d stream fd with poll/read, local counter reservation via per-context state= , and conflict resolution between the two. The memory barrier usage for the= FIFO follows the kernel's documented circ_buf producer/consumer pattern co= rrectly. The locking hierarchy (gpu->lock before perfcntr_lock) is handled = carefully with appropriate comments about deadlock avoidance in the suspend= /release paths. I have a few concerns, mostly minor, detailed per-patch below. --- Generated by Claude Code Patch Reviewer