From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: DSC max delta bpp support Date: Thu, 28 May 2026 12:24:07 +1000 Message-ID: In-Reply-To: <20260527110849.3943338-1-nemesa.garg@intel.com> References: <20260527110849.3943338-1-nemesa.garg@intel.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Overall Series Review Subject: DSC max delta bpp support Author: Nemesa Garg Patches: 5 Reviewed: 2026-05-28T12:24:07.251231 --- This 4-patch series adds support for decoding DSC maximum bpp from the delta-based DPCD field (register 0x06E) for DP sinks that expose this capability. The series is logically structured: fix the register placement in drm_dp.h, rename for spec alignment, add computation constants, then use them in intel_dp.c. The concept is sound and the patches are a reasonable size. However, there are several issues worth flagging: the YCbCr422 mask is placed under the wrong register, there's a potential logic bug where an out-of-range delta value silently returns an uninitialized-looking result, and the naming of the new delta constants is inconsistent. --- --- Generated by Claude Code Patch Reviewer